公开(公告)号：US20150333716A1

公开(公告)日：2015-11-19

申请号：US14275897

申请日：2014-05-13

Applicant: MEDIATEK INC.

Inventor： Tze-Chien Wang

IPC: H03G1/00 ,  H03F1/26

CPC classification number: H03G1/0088 ,  H03F1/0277 ,  H03F1/26 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/372 ,  H03F2201/3206 ,  H03F2203/7215 ,  H03F2203/7221 ,  H03F2203/7236

Abstract: A method and an apparatus for performing signal amplifying with aid of switching control are provided, where the method may include the steps of: modulating an input signal of a gain stage based on one of several modulation schemes to generate at least one first amplified result of a first amplifying path of the gain stage; modulating the input signal of the gain stage based on one of the several modulation schemes to generate at least one second amplified result of a second amplifying path of the gain stage; and generating an amplified signal of the gain stage based on at least the first amplified result and the second amplified result. In addition, at least one switching time point of the first amplifying path for switching between the several modulation schemes and one switching time point of the second amplifying path for switching between the several modulation schemes are non-overlapped.

Abstract translation: 提供了一种借助于切换控制来进行信号放大的方法和装置，其中该方法可以包括以下步骤：基于若干调制方案之一调制增益级的输入信号，以产生至少一个第一放大结果 增益级的第一放大路径; 基于所述多个调制方案之一调制所述增益级的输入信号，以生成所述增益级的第二放大路径的至少一个第二放大结果; 以及至少基于第一放大结果和第二放大结果生成增益级的放大信号。 此外，用于在几个调制方案之间切换的第一放大路径的至少一个切换时间点和用于在若干调制方案之间切换的第二放大路径的一个切换时间点是非重叠的。

公开(公告)号：US09490835B2

公开(公告)日：2016-11-08

申请号：US14603590

申请日：2015-01-23

Applicant: MediaTek Inc.

Inventor： Tze-Chien Wang

IPC: H03M3/00

CPC classification number: H03M3/37 ,  H03M3/458

Abstract: A modulation circuit includes a digital quantizer and a compensation circuit. The digital quantizer is utilized to receive and truncate a digital quantizing input signal for generating a digital quantizing output signal. The compensation circuit compensates for a time delay of the modulation circuit and generates a compensation output signal. The digital quantizing input signal is generated by subtracting the compensation output signal from a digital integration output signal to compensate for the time delay before truncating the digital quantizing input signal.

Abstract translation: 调制电路包括数字量化器和补偿电路。 数字量化器用于接收和截取用于产生数字量化输出信号的数字量化输入信号。 补偿电路补偿调制电路的时间延迟并产生补偿输出信号。 数字量化输入信号通过从数字积分输出信号中减去补偿输出信号来产生，以补偿在截断数字量化输入信号之前的时间延迟。

公开(公告)号：US10461702B2

公开(公告)日：2019-10-29

申请号：US15911187

申请日：2018-03-05

Applicant: MEDIATEK INC.

Inventor： Tsun-Yuan Fan ,  Tze-Chien Wang

IPC: H03F1/34 ,  H03F3/45 ,  H03F1/32 ,  H01L49/02

Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an operational amplifier and a feedback path. The operational amplifier has an input terminal and an output terminal, and is arranged for receiving an input signal to generate an output signal. The feedback path is coupled between the input terminal and the output terminal of the operational amplifier, wherein the feedback path comprises at least two poly resistors, and a depletion region of at least one of the two poly resistors is biased by the output signal generated by the operational amplifier.

公开(公告)号：US09806703B2

公开(公告)日：2017-10-31

申请号：US15338628

申请日：2016-10-31

Applicant: MediaTek Inc.

Inventor： Yu-Hsin Lin ,  Tze-Chien Wang

IPC: H03L5/00 ,  H03K5/02

CPC classification number: H03K5/02 ,  H03F1/26 ,  H03F3/26 ,  H03F3/45475 ,  H03F3/45928 ,  H03F2200/06 ,  H03F2200/261 ,  H03F2200/78 ,  H03F2203/45138 ,  H03F2203/45594

Abstract: A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

公开(公告)号：US09537497B2

公开(公告)日：2017-01-03

申请号：US15044125

申请日：2016-02-16

Applicant: MEDIATEK INC.

Inventor： Chen-Yen Ho ,  Yu-Hsin Lin ,  Tze-Chien Wang

IPC: H03M1/00 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03M1/06 ,  H03M3/37 ,  H03M3/422 ,  H03M3/464

Abstract: A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit.

Abstract translation: 连续时间ΔΣ调制器包括求和电路，环路滤波器，提取电路，量化器和数模转换器。 求和电路被布置为通过输入信号减去反馈信号以产生残余信号。 环路滤波器包括串联连接的多个放大级，并被布置为接收残余信号以产生滤波的残留信号。 提取电路被布置为从一个放大级提取电流，并将提取的电流转发到下一个放大级。 量化器被布置用于根据滤波的残留信号产生数字输出信号。 数模转换器被配置为根据从数字输出信号导出的信号执行数模转换操作，以产生到求和电路的反馈信号。

公开(公告)号：US20230228813A1

公开(公告)日：2023-07-20

申请号：US17989696

申请日：2022-11-18

Applicant: MEDIATEK INC.

Inventor： Tze-Chien Wang

IPC: G01R31/317 ,  G01R31/3181 ,  G01R19/165

CPC classification number: G01R31/31721 ,  G01R31/31816 ,  G01R19/16552 ,  H02M1/325

Abstract: The present invention provides a glitch detector including a first inverter, a second inverter, a first capacitor and a second capacitor. The first inverter is connected between a supply voltage and a ground voltage, and is configured to receive a first signal at a first node to generate a second signal to a second node. The second inverter is connected between the supply voltage and the ground voltage, and is configured to receive the second signal at the second node to generate the first signal to the first node. A first electrode of the first capacitor is coupled to the supply voltage, and a second electrode of the first capacitor is coupled to the first node. A first electrode of the second capacitor is coupled to the ground voltage, and a second electrode of the second capacitor is coupled to the second node.

公开(公告)号：US20180309415A1

公开(公告)日：2018-10-25

申请号：US15911187

申请日：2018-03-05

Applicant: MEDIATEK INC.

Inventor： Tsun-Yuan Fan ,  Tze-Chien Wang

IPC: H03F1/34 ,  H03F3/45

Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an operational amplifier and a feedback path. The operational amplifier has an input terminal and an output terminal, and is arranged for receiving an input signal to generate an output signal. The feedback path is coupled between the input terminal and the output terminal of the operational amplifier, wherein the feedback path comprises at least two poly resistors, and a depletion region of at least one of the two poly resistors is biased by the output signal generated by the operational amplifier.

公开(公告)号：US09559674B2

公开(公告)日：2017-01-31

申请号：US15044114

申请日：2016-02-16

Applicant: MEDIATEK INC.

Inventor： Chen-Yen Ho ,  Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Tze-Chien Wang

IPC: H03M1/00 ,  H03K3/356 ,  H03M1/08 ,  H03M1/66

CPC classification number: H03K3/356113 ,  H03K3/356121 ,  H03K3/356191 ,  H03M1/066 ,  H03M1/0872 ,  H03M1/66 ,  H03M3/464

Abstract: A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

Abstract translation: 锁存电路包括输入级，放大级和时钟门控电路。 输入级被布置成用于接收至少一个时钟信号和数据控制信号。 放大级与输入级耦合，由供电电压和接地电压提供，并被配置为保持数据值并根据时钟信号和数据控制信号输出数据值。 时钟门控电路耦合到放大级，并且被布置为避免电源电压和接地电压之间的短路电流。