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    METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL
    5.
    发明申请
    METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL 有权
    具有包含单个半导体通道的记忆细胞的方法和装置

    公开(公告)号：US20150123189A1

    公开(公告)日：2015-05-07

    申请号：US14069574

    申请日：2013-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

    Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

    3-D Memory Arrays
    7.
    发明申请
    3-D Memory Arrays 有权
    3-D内存数组

    公开(公告)号：US20140217488A1

    公开(公告)日：2014-08-07

    申请号：US13759627

    申请日：2013-02-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

    IPC: H01L29/78

    CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

    Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，这些栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

    Integrated structures
    8.
    发明授权
    Integrated structures 有权

    公开(公告)号：US09659949B2

    公开(公告)日：2017-05-23

    申请号：US14666002

    申请日：2015-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

    IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

    3-D memory arrays
    10.
    发明授权
    3-D memory arrays 有权
    3-D存储器阵列

    公开(公告)号：US09219070B2

    公开(公告)日：2015-12-22

    申请号：US13759627

    申请日：2013-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

    IPC: H01L29/41 ,  H01L29/417 ,  H01L27/115 ,  H01L27/02 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

    Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，该栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

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