公开(公告)号：US11424256B2

公开(公告)日：2022-08-23

申请号：US16662945

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/16 ,  H01L29/66 ,  H01L21/283 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

公开(公告)号：US09082772B2

公开(公告)日：2015-07-14

申请号：US14085361

申请日：2013-11-20

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L29/76 ,  H01L29/788 ,  H01L23/552 ,  H01L23/535 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US20210005624A1

公开(公告)日：2021-01-07

申请号：US17012297

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US20200058662A1

公开(公告)日：2020-02-20

申请号：US16662945

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L27/11524 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L29/10 ,  H01L27/11556 ,  H01L21/283 ,  H01L29/49 ,  H01L29/16 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/78

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

公开(公告)号：US10269626B2

公开(公告)日：2019-04-23

申请号：US15867017

申请日：2018-01-10

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11575

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

公开(公告)号：US09557376B2

公开(公告)日：2017-01-31

申请号：US15069316

申请日：2016-03-14

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L29/78

CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

公开(公告)号：US09508591B2

公开(公告)日：2016-11-29

申请号：US14797390

申请日：2015-07-13

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L21/461 ,  H01L21/768 ,  H01L27/105 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

公开(公告)号：US20150318203A1

公开(公告)日：2015-11-05

申请号：US14797390

申请日：2015-07-13

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US20140138840A1

公开(公告)日：2014-05-22

申请号：US14085361

申请日：2013-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US20170162589A1

公开(公告)日：2017-06-08

申请号：US15439282

申请日：2017-02-22

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L27/11524 ,  H01L29/788 ,  H01L29/10 ,  H01L27/11556 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11524 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.