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公开(公告)号：US20240154607A1
公开(公告)日：2024-05-09
申请号：US17983738
申请日：2022-11-09
Applicant: Macronix International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
CPC classification number: H03K3/037 , G06F13/1684 , G11C16/10 , G11C16/32 , H03K5/13 , H03K19/21 , G11C16/0483
Abstract: Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.
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公开(公告)号：US20250105833A1
公开(公告)日：2025-03-27
申请号：US18475239
申请日：2023-09-27
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
Abstract: A duty cycle correction method and a duty cycle correction apparatus, adapted for correcting a duty cycle of a clock signal by using a duty cycle adjuster in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, the duty cycle is adjusted and input to data pads to generate data signals, wherein the data pads are divided into at least two groups and defined by data patterns that are inverse to each other; DC voltages of the data signals of a first group of data pads are detected to generate a first average DC voltage, and DC voltages of the data signals of a second group of data pads are detected to generate a second average DC voltage, the aforementioned average DC voltages are compared, and the duty cycle adjuster is controlled to adjust the duty cycle of the clock signal.
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公开(公告)号：US20250104750A1
公开(公告)日：2025-03-27
申请号：US18475246
申请日：2023-09-27
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
Abstract: A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device is a 3D NAND flash with high capacity and high performance. The calibration apparatus includes an impedance, a strong-arm comparator, a logic circuit, and a calibration controller. The impedance is configured to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares a reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. The calibration controller implements an impedance calibration in the memory device according to the comparison result signal.
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公开(公告)号：US12166486B2
公开(公告)日：2024-12-10
申请号：US17983738
申请日：2022-11-09
Applicant: Macronix International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
Abstract: Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.
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