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    Semiconductor devices having vertical channel transistors and methods for fabricating the same
    1.
    发明授权
    Semiconductor devices having vertical channel transistors and methods for fabricating the same 有权
    具有垂直沟道晶体管的半导体器件及其制造方法

    公开(公告)号：US08742493B2

    公开(公告)日：2014-06-03

    申请号：US13285263

    申请日：2011-10-31

    申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

    发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

    摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

    摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

    SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME 有权
    具有垂直通道晶体管的半导体器件及其制造方法

    公开(公告)号：US20120119286A1

    公开(公告)日：2012-05-17

    申请号：US13285263

    申请日：2011-10-31

    申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

    发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

    摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

    摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

    Semiconductor devices with vertical channel transistors
    6.
    发明授权
    Semiconductor devices with vertical channel transistors 有权
    具有垂直沟道晶体管的半导体器件

    公开(公告)号：US09111960B2

    公开(公告)日：2015-08-18

    申请号：US13242660

    申请日：2011-09-23

    申请人： Hui-Jung Kim ,  Yongchul Oh ,  Daeik Kim ,  Hyun-Woo Chung

    发明人： Hui-Jung Kim ,  Yongchul Oh ,  Daeik Kim ,  Hyun-Woo Chung

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/108

    CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L29/7827

    摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.

    摘要翻译： 具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案， 第一门模式。 第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

    Integrated circuit devices including low-resistivity conductive patterns in recessed regions
    7.
    发明授权
    Integrated circuit devices including low-resistivity conductive patterns in recessed regions 有权
    集成电路器件包括凹陷区域中的低电阻率导电图案

    公开(公告)号：US08294131B2

    公开(公告)日：2012-10-23

    申请号：US12826896

    申请日：2010-06-30

    申请人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    发明人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/2454 ,  H01L27/2463

    摘要： An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

    摘要翻译： 集成电路器件包括在半导体衬底上的器件隔离图案，以在其中限定有效区域。 有源区域包括其中的掺杂区域。 导电图案在有源区上延伸并与掺杂区电接触。 导电图案具有比掺杂区域更低的电阻率。 导电图案可以设置在具有低于有源区域的顶表面的底表面的凹陷区域中。 通道柱与掺杂区电接触并从远离衬底的方向从其延伸。 导电栅电极设置在通道柱的侧壁上，并且栅极电介质层设置在沟道柱的栅电极和侧壁之间。

    Vertical pillar transistor
    9.
    发明申请
    Vertical pillar transistor 有权
    立柱晶体管

    公开(公告)号：US20090242975A1

    公开(公告)日：2009-10-01

    申请号：US12382898

    申请日：2009-03-26

    申请人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

    发明人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/10882 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

    摘要： A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.

    摘要翻译： 垂直柱状晶体管可以包括多个下部支柱，多个上部支柱，第一绝缘部分，第二绝缘部分和字线。 多个下支柱基本上垂直于基板突出并且由多个沟槽限定。 多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。 多个上柱可以形成在多个下支柱上。 多个上支柱具有比多个下支柱的宽度更小的宽度。 第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。 第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。 字线可以形成在第二绝缘部分上，并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。