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    Dynamic semiconductor memory device having a trench capacitor
    5.
    发明授权
    Dynamic semiconductor memory device having a trench capacitor 失效
    具有沟槽电容器的动态半导体存储器件

    公开(公告)号：US06720606B1

    公开(公告)日：2004-04-13

    申请号：US09660390

    申请日：2000-09-12

    申请人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

    发明人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/945

    摘要： A semiconductor memory device has a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitors having a trench extends through the first semiconductor region and the second semiconductor region, and is formed such that its top does not reach a top surface of the second semiconductor region, and the trench is formed therein with a conductive trench fill. A pair of gate electrodes is formed on the second semiconductor region, overlying the trench capacitor. A pair of insulating layers is formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.

    摘要翻译： 半导体存储器件具有形成在第一半导体区域上的半导体衬底，形成在半导体衬底上的第一导电类型的第一半导体区域，与第一导电类型相反的第二导电类型的第二半导体区域。 具有沟槽的沟槽电容器延伸穿过第一半导体区域和第二半导体区域，并且形成为使得其顶部不到达第二半导体区域的顶表面，并且沟槽在其中形成有导电沟槽填充物。 在第二半导体区上形成一对栅电极，覆盖在沟槽电容器上。 形成一对绝缘层以覆盖该对栅电极中的每一个。 在一对绝缘层之间形成导电层，以与一对绝缘层中的每一个自对准。 导电层具有与第二半导体区域绝缘​​并到达第二半导体区域的内部的前端，并且电连接到沟槽电容器的导电沟槽填充物。 第一导电类型的一对第三半导体区域形成在第二半导体区域中，并且相对于导电层彼此相对定位。 第三半导体区域中的每一个直接与导电层接触，并且分别构成具有一对栅极电极之一的晶体管的源极或漏极。 一对第三半导体区域基本上形成为均匀的深度。

    Dynamic semiconductor memory device having a trench capacitor
    6.
    发明授权
    Dynamic semiconductor memory device having a trench capacitor 失效
    具有沟槽电容器的动态半导体存储器件

    公开(公告)号：US06236079B1

    公开(公告)日：2001-05-22

    申请号：US08982478

    申请日：1997-12-02

    申请人： Akihiro Nitayama ,  Katsuhiko Hieda

    发明人： Akihiro Nitayama ,  Katsuhiko Hieda

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/945

    摘要： A semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bit lines are formed on the semiconductor substrate and extend in a second direction. An isolated active areas are formed on the semiconductor substrate under the second bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain regions and the third word line being insulatively spaced from a channel region between the source and drain regions. A first storage node is formed in a portion of the semiconductor substrate which is between the first and second word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line. A second storage node is formed in a portion of the semiconductor substrate which is between the third and fourth word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line.

    摘要翻译： 半导体存储器件包括半导体衬底和形成在半导体衬底上并沿第一方向延伸的第一，第二，第三和第四间隔开的字线。 第一，第二和第三间隔开的位线形成在半导体衬底上并沿第二方向延伸。 在第二位线下的半导体衬底上形成隔离的有源区。 第一传输门晶体管形成在有源区中，第一传输栅极晶体管包括间隔开的源极和漏极区，并且第二字线与源极和漏极区之间的沟道区域间隔开。 第二传输门晶体管形成在有源区中，第二传输栅极晶体管包括间隔开的源极和漏极区，并且第三字线与源区和漏区之间的沟道区域间隔开。 第一存储节点形成在半导体衬底的位于第一和第二字线之间，第一位线和第二位线之间，第二位线下方以及第二位线和第三位线之间的部分中。 第二存储节点形成在半导体衬底的位于第三和第四字线之间，第一位线和第二位线之间，第二位线之下以及第二位线和第三位线之间的部分中。

    Semiconductor memory device and method for manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US06707706B2

    公开(公告)日：2004-03-16

    申请号：US10183156

    申请日：2002-06-28

    申请人： Akihiro Nitayama ,  Katsuhiko Hieda

    发明人： Akihiro Nitayama ,  Katsuhiko Hieda

    IPC分类号： G11C1124

    CPC分类号： H01L27/10876 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L28/90

    摘要： A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.

    摘要翻译： 半导体存储器件包括形成在半导体衬底上的存储单元阵列区域中的多个柱状部分。 柱状部分通过多个沟槽彼此隔离，并且这些沟槽具有深度不同的第一和第二底部。 半导体器件包括多个单元晶体管，其包括形成在第一底部的第一扩散层区域，其比第二底部浅，形成在柱状部分的表面部分中的第二扩散层区域和多个栅电极 邻近第一和第二扩散层区域并且沿着柱状部分的至少一个侧表面部分延伸。

    Method of making dynamic random access semiconductor memory device
    8.
    发明授权
    Method of making dynamic random access semiconductor memory device 失效
    制作动态随机存取半导体存储器件的方法

    公开(公告)号：US5350708A

    公开(公告)日：1994-09-27

    申请号：US77744

    申请日：1993-06-18

    申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10841 ,  H01L27/10823

    摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

    摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的

    Dynamic type semiconductor memory device and its manufacturing method
    10.
    发明授权
    Dynamic type semiconductor memory device and its manufacturing method 失效
    动态型半导体存储器件及其制造方法

    公开(公告)号：US5250830A

    公开(公告)日：1993-10-05

    申请号：US797192

    申请日：1991-11-25

    申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

    CPC分类号： H01L27/10841 ,  H01L27/10823

    摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

    摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的