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1.发明授权Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统公开(公告)号：US07625807B2
公开(公告)日：2009-12-01
申请号：US11678107
申请日：2007-02-23
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译： 本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。 通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。 保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。 结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。 此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。
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2.发明授权Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译： 具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。
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3.发明授权公开(公告)号：US07199021B2
公开(公告)日：2007-04-03
申请号：US10874038
申请日：2004-06-22
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
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4.发明申请公开(公告)号：US20120164820A1
公开(公告)日：2012-06-28
申请号：US13404840
申请日：2012-02-24
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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5.发明授权公开(公告)号：US08124529B2
公开(公告)日：2012-02-28
申请号：US11421671
申请日：2006-06-01
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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公开(公告)号：US08062966B2
公开(公告)日：2011-11-22
申请号：US12647074
申请日：2009-12-24
申请人： Freido Mehrad , James J. Chambers , Shaofeng Yu
发明人： Freido Mehrad , James J. Chambers , Shaofeng Yu
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823842 , H01L29/66545 , H01L29/6659
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.
摘要翻译： 提供半导体器件和制造方法，其中为CMOS晶体管提供金属晶体管替代栅极。 该过程在CMOS工艺中提供双重或差分工作功能能力（例如，用于PMOS和NMOS晶体管）。
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公开(公告)号：US07528024B2
公开(公告)日：2009-05-05
申请号：US10890365
申请日：2004-07-13
IPC分类号： H01L21/28 , H01L21/338 , H01L21/44
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
摘要翻译： 本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。 该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。 金属层的功函数与半导体衬底的导带或价带相匹配。 该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。 对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。 本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。
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8.发明授权Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes 有权用双功能金属栅电极制造自对准晶体管的结构和方法公开(公告)号：US07005365B2
公开(公告)日：2006-02-28
申请号：US10649425
申请日：2003-08-27
申请人： James J. Chambers
发明人： James J. Chambers
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66583 , H01L21/28079 , H01L21/823842 , H01L29/6659 , H01L29/7833
摘要： The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method includes forming a gate dielectric (105) over a substrate (110) and depositing a mold layer (115) having a first opening (120) therein over the gate dielectric (105). The method further includes creating a first metal gate electrode (125) by depositing a first metal in the first opening (120). Other embodiments include an active device (200) produced by the above-described method and method of manufacturing an integrated circuit (300) using the above-described method.
摘要翻译： 本发明在一个实施例中提供了在半导体器件中形成双功函数金属栅电极的方法（100）。 该方法包括在衬底（110）上形成栅极电介质（105），并且在栅极电介质（105）上沉积其中具有第一开口（120）的模具层（115）。 该方法还包括通过在第一开口（120）中沉积第一金属来产生第一金属栅电极（125）。 其他实施例包括通过上述使用上述方法制造集成电路（300）的方法和方法产生的有源器件（200）。
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公开(公告)号：US06936508B2
公开(公告)日：2005-08-30
申请号：US10661130
申请日：2003-09-12
申请人： Mark Visokay , Luigi Colombo , James J. Chambers
发明人： Mark Visokay , Luigi Colombo , James J. Chambers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205 , H01L29/76
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517 , H01L29/665
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.
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10.发明授权Reliable high voltage gate dielectric layers using a dual nitridation process 有权使用双重氮化工艺的可靠的高压栅极电介质层公开(公告)号：US07560792B2
公开(公告)日：2009-07-14
申请号：US11626624
申请日：2007-01-24
申请人： Rajesh Khamankar , Douglas T. Grider , Hiroaki Niimi , April Gurba , Toan Tran , James J. Chambers
发明人： Rajesh Khamankar , Douglas T. Grider , Hiroaki Niimi , April Gurba , Toan Tran , James J. Chambers
IPC分类号： H01L27/105
CPC分类号： H01L21/823462 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).
摘要翻译： 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质层上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。
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