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    Self-aligned transistor device including a patterned refracting dielectric layer
    1.
    发明授权
    Self-aligned transistor device including a patterned refracting dielectric layer 失效
    自对准晶体管器件包括图案折射介电层

    公开(公告)号：US5814859A

    公开(公告)日：1998-09-29

    申请号：US558297

    申请日：1995-11-15

    申请人： Mario Ghezzo ,  Tat-Sing Paul Chow ,  James William Kretchmer ,  Richard Joseph Saia ,  William Andrew Hennessy

    发明人： Mario Ghezzo ,  Tat-Sing Paul Chow ,  James William Kretchmer ,  Richard Joseph Saia ,  William Andrew Hennessy

    IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L31/0312 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/1608 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802

    摘要： A semiconductor device includes a semiconductor substrate having an epitaxial layer surface opposite a drain contact surface; a semiconductor layer adjacent to the epitaxial layer surface of the substrate, the semiconductor layer including material of a first conductivity type; a patterned refractory dielectric layer adjacent to the semiconductor layer; a base region of implanted ions in the semiconductor layer, the base region being of a second conductivity type; a source region of implanted ions in the base region, the source region being of the first conductivity type; a gate insulator layer adjacent to at least a portion of the source and base regions of the semiconductor layer; and a gate electrode over a portion of the gate insulator layer, adjacent to and in physical contact with an outer edge of the patterned refractory dielectric layer, and over at least a portion of the base region between the source region and the patterned refractory dielectric layer.

    摘要翻译： 半导体器件包括具有与漏极接触表面相对的外延层表面的半导体衬底; 与衬底的外延层表面相邻的半导体层，所述半导体层包括第一导电类型的材料; 与半导体层相邻的图案化耐火介电层; 所述半导体层中的注入离子的基极区域，所述基极区域是第二导电类型; 在所述基极区域中的注入离子的源极区域，所述源极区域是所述第一导电类型; 与所述半导体层的源极和基极区域的至少一部分相邻的栅极绝缘体层; 以及在所述栅极绝缘体层的与所述图案化耐火介电层的外边缘相邻并物理接触的部分上的栅电极以及所述源极区域和所述图案化耐火介电层之间的所述基极区域的至少一部分 。

    Transistor
    2.
    发明授权
    Transistor 有权
    晶体管

    公开(公告)号：US08188514B2

    公开(公告)日：2012-05-29

    申请号：US12540230

    申请日：2009-08-12

    申请人： Masahiro Sugimoto ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Tetsu Kachi ,  Tsutomu Uesugi

    发明人： Masahiro Sugimoto ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Tetsu Kachi ,  Tsutomu Uesugi

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7788

    摘要： An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

    摘要翻译： 公开了一种HEMT型晶体管，其是常闭型，栅极阈值电压的变化小。 晶体管设置有p型区域，势垒区域，绝缘膜，栅极电极。 沟道区域连接到p型区域的上表面。 通道区域是n型或i型，并且设置有第一通道区域和第二通道区域。 阻挡区域与第一通道区域的上表面形成异质结。 绝缘膜连接到第二通道区域的上表面和阻挡区域的上表面。 栅电极经由绝缘膜面向第二沟道区和阻挡区。 第一通道区域和第二通道区域在电流通路中串联布置。

    Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same
    5.
    发明授权
    Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same 有权
    具有多区域结终止延伸的半导体器件及其制造方法

    公开(公告)号：US07144797B2

    公开(公告)日：2006-12-05

    申请号：US10949982

    申请日：2004-09-24

    申请人： Tat-Sing Paul Chow ,  Peter Losee ,  Santhosh Balachandran

    发明人： Tat-Sing Paul Chow ,  Peter Losee ,  Santhosh Balachandran

    IPC分类号： H01L21/22 ,  H01L21/425 ,  H01L21/332

    CPC分类号： H01L21/0465 ,  H01L21/2652 ,  H01L29/6606

    摘要： A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.

    摘要翻译： 半导体器件包括分级结终止延伸。 一种制造该器件的方法包括提供具有pn结的半导体层，提供与半导体层相邻的掩模层，蚀刻掩模层以形成与不同掩模厚度和基本上平面的台阶表面相关联的至少两个横向相邻的步骤，以及 将掺杂剂物质通过掩模层注入到与pn结的端接点相邻的半导体层的一部分中。 半导体层被退火以激活至少一部分注入的掺杂物种以形成分级结终止延伸。

    TRANSISTOR
    6.
    发明申请
    TRANSISTOR 有权
    晶体管

    公开(公告)号：US20100038681A1

    公开(公告)日：2010-02-18

    申请号：US12540230

    申请日：2009-08-12

    申请人： Masahiro SUGIMOTO ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Totsu Kachi ,  Tsutomu Uesugi

    发明人： Masahiro SUGIMOTO ,  Tat-Sing Paul Chow ,  Zhongda Li ,  Totsu Kachi ,  Tsutomu Uesugi

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7787 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7788

    摘要： An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

    摘要翻译： 公开了一种HEMT型晶体管，其是常闭型，栅极阈值电压的变化小。 晶体管设置有p型区域，势垒区域，绝缘膜，栅极电极。 沟道区域连接到p型区域的上表面。 通道区域是n型或i型，并且设置有第一通道区域和第二通道区域。 阻挡区域与第一通道区域的上表面形成异质结。 绝缘膜连接到第二通道区域的上表面和阻挡区域的上表面。 栅电极经由绝缘膜面向第二沟道区和阻挡区。 第一通道区域和第二通道区域在电流通路中串联布置。

    Method to enhance operating characteristics of FET, IGBT, and MCT structures
    7.
    发明授权
    Method to enhance operating characteristics of FET, IGBT, and MCT structures 失效
    增强FET，IGBT和MCT结构的工作特性的方法

    公开(公告)号：US06656774B1

    公开(公告)日：2003-12-02

    申请号：US08310041

    申请日：1994-09-22

    申请人： Tat-Sing Paul Chow ,  Victor Albert Keith Temple

    发明人： Tat-Sing Paul Chow ,  Victor Albert Keith Temple

    IPC分类号： H01L21332

    CPC分类号： H01L29/7802 ,  H01L29/167 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7813

    摘要： Doping of the P type base region in a MOSFET or an IGBT with a combination of boron and one or more of indium, aluminum and gallium, provides a structure having a lower P type doping level in the channel portion of the structure than in the remainder of the structure without requiring counter doping of the channel. The doping level of the emitter region of an MCT is kept high everywhere except in the channel in order to provide a fast turn-off time for the MCT.

    摘要翻译： 在MOSFET或具有硼与铟，铝和镓中的一种或多种的组合的IGBT中的P型基极区域的掺杂提供了在结构的沟道部分中具有比在其余部分中的P型掺杂浓度低的结构 的结构，而不需要反向掺杂通道。 MCT的发射极区域的掺杂水平保持高位，除了通道以外，为了提供MCT的快速关断时间。