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公开(公告)号：US07511299B1
公开(公告)日：2009-03-31
申请号：US11906669
申请日：2007-10-02
IPC分类号： H01L23/58
CPC分类号： H01L23/66 , H01L22/32 , H01L2223/6627 , H01L2224/16 , H01L2924/15311 , H01L2924/1903 , H01L2924/19105 , H01L2924/3011
摘要： A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.
摘要翻译： 封装集成电路（“IC”）包括基板，IC管芯和模制塑料盖。 测试点间隔电连接到IC管芯，并通过模塑塑料盖朝模塑塑料盖的顶表面远离封装衬底的表面延伸。 测试点支架的顶部位于模制塑料盖的顶部表面之下。
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公开(公告)号：US08258845B1
公开(公告)日：2012-09-04
申请号：US11134117
申请日：2005-05-20
申请人： Mark A. Alexander , Sean A. Koontz
发明人： Mark A. Alexander , Sean A. Koontz
IPC分类号： H03K3/00
摘要： The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.
摘要翻译： 响应于设备电源电压的波动来动态地调节IC器件的电路块触发开关事件的相对定时，以最小化由电源电压噪声引起的时钟抖动。 控制电路监视电源电压波动，响应于此，动态地相移触发切换事件的时钟信号，使得在电源电压波动最小的相对安静的时间间隔期间发生开关事件。
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公开(公告)号：US08086435B1
公开(公告)日：2011-12-27
申请号：US12333151
申请日：2008-12-11
申请人： Mark A. Alexander
发明人： Mark A. Alexander
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.
摘要翻译： 一种用于预测由电气系统内的一个或多个信号传导路径产生的同时开关输出（SSO）噪声的方法。 首先为可能受电扰动影响的每个信号传导路径记录电扰动波形。 接下来，利用叠加原理来相干地组合时域中的每个电扰动波形，以产生施加在受影响的信号传导路径上的预测的SSO噪声波形。 可以通过使用在实际集成电路上进行的台架测量，通过模拟或通过模拟和台架测量的组合来产生电扰动波形。
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4.发明授权公开(公告)号：US06961231B1
公开(公告)日：2005-11-01
申请号：US11074967
申请日：2005-03-08
CPC分类号： H01G4/232 , H01G4/35 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H01L2924/19103 , H05K1/0231 , H05K1/141 , H05K1/162 , H05K2201/09309 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734
摘要： Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.
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5.发明申请Attenuating Non-Linear Noise in An Amplifier with Alternating DC -offset Correction 有权具有交替DC偏移校正的放大器中的衰减非线性噪声公开(公告)号：US20130088294A1
公开(公告)日：2013-04-11
申请号：US13595141
申请日：2012-08-27
CPC分类号： H03G3/3026 , H03F1/26 , H03F3/185 , H03F3/189 , H03F3/2173 , H03F3/45 , H03F3/45179 , H03F2200/03 , H03G1/04 , H03K5/003
摘要： An amplifier may include two or more pulse-width modulators controlling respective sets of switches to produce an amplified version of a source signal. A positive DC-offset based on the source signal may be applied to the pulse-width modulator controlling one respective set of switches, and an equal value negative DC-offset may be applied to the pulse-width modulator controlling the other respective set of switches, to provide an effective offset between the respective points in time of the rising/falling edges of the different pulse-width modulated control signals. The addition of alternating positive and negative DC-offset values doesn't affect the output load, and doesn't degrade the signal. The DC-offsets may be added at a frequency selected to be beyond the signal baseband, and the value of the small input signal level may be determined using an RMS level comparator or similar measurement technique.
摘要翻译： 放大器可以包括两个或更多个脉冲宽度调制器，其控制各组开关以产生源信号的放大版本。 可以将基于源极信号的正DC偏移施加到控制一组相应开关的脉冲宽度调制器，并且可以将相等值的负DC偏移施加到控制另一组开关的脉宽调制器 以提供不同脉冲宽度调制控制信号的上升/下降沿的各个时间点之间的有效偏移。 交替的正和负DC偏移值的添加不会影响输出负载，也不会降低信号。 可以以选择为超出信号基带的频率添加DC偏移，并且可以使用RMS电平比较器或类似的测量技术来确定小输入信号电平的值。
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公开(公告)号：US20100244802A1
公开(公告)日：2010-09-30
申请号：US12815609
申请日：2010-06-15
申请人： Mark A. Alexander
发明人： Mark A. Alexander
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , H02M1/38 , H02M2001/008
摘要： Transient processing mechanisms for power converters. Error generation circuitry in a power converter may generate an error signal based on the difference between a power converter output voltage and a reference voltage. Transient detection circuitry may detect whether the error signal exceeds at least a first threshold. If the first threshold is exceeded, timing control logic may generate a low band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the first threshold. If the error signal exceeds a second threshold, the timing control logic may generate a high band correction pulse to adjust the power converter output voltage, and thereby adjust the error signal to a level within the second threshold. The timing control logic may initiate a low band blanking period following the low band correction pulse and high band blanking period following the high band correction pulse.
摘要翻译： 电源转换器的瞬态处理机制。 功率转换器中的误差产生电路可以基于功率转换器输出电压和参考电压之间的差异产生误差信号。 瞬态检测电路可以检测误差信号是否超过至少第一阈值。 如果超过第一阈值，则定时控制逻辑可以产生低频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第一阈值内的电平。 如果误差信号超过第二阈值，则定时控制逻辑可以产生高频带校正脉冲以调整功率转换器输出电压，从而将误差信号调整到第二阈值内的电平。 定时控制逻辑可以在高频带校正脉冲和高频带校正脉冲之后的低频带校正脉冲和高频带消隐周期之后发起低频消隐周期。
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7.发明授权公开(公告)号：US07239257B1
公开(公告)日：2007-07-03
申请号：US11376888
申请日：2006-03-16
CPC分类号： H02M3/157
摘要： A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.
摘要翻译： 一种功率转换器，包括硬件高效的控制环路架构。 误差检测电路可以基于功率转换器输出电压和参考电压之间的差异产生误差信号。 过采样ADC可以将误差信号数字化。 与ADC相关联的传递函数可以包括以与中心码不同的间隔隔开的量化级别。 数字滤波器可以计算数字化误差信号的平均值。 非线性再量化器可以减少与数字滤波器的输出相对应的代码数量。 比例积分微分（PID）单元可以通过PID系数乘以非线性重组器的输出，以产生PID占空比命令，增益补偿单元可以动态地调整PID系数以保持恒定的控制环路增益。 包括多电平误差反馈Δ-Σ调制器的噪声形截断单元可以降低PID占空比指令的分辨率。
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8.发明申请Noise and Cross-Talk Attenuation in an Audio System by Offsetting Outputs in Phase 审中-公开音频系统中的噪声和串扰衰减通过在相位上偏移输出公开(公告)号：US20150063593A1
公开(公告)日：2015-03-05
申请号：US14490459
申请日：2014-09-18
CPC分类号： H03G3/3026 , H03F1/26 , H03F3/185 , H03F3/189 , H03F3/2173 , H03F3/45 , H03F3/45179 , H03F2200/03 , H03G1/04 , H03K5/003
摘要： An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.
摘要翻译： 放大器可以包括两个或更多个脉冲宽度调制器（PWM），其控制各组开关以产生源信号的放大版本。 可以控制放大器的时钟，以在时间上相对于彼此延迟PWM内的信号处理，从而在控制信号的边沿转换到相应的开关组之间的绝对时刻之间提供有效的时间偏移。 当检测到新的数据样本时，PWM可以包括从下一个PWM占空比值向下递减到零的递减器，当存在下一个采样时，开始新的计数。 PWM输出可对应于计数器值，当计数器值不为零时输出脉冲。 可以从主计数器解码“数据采样就绪”信号，该主计数器可以基于高速PWM时钟来计时，并且延迟机制可以基于调整解码值来确定PWM何时应该初始化为 下一个数据样本。
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公开(公告)号：US07755381B1
公开(公告)日：2010-07-13
申请号：US12359902
申请日：2009-01-26
申请人： Peter H. Alfke , Mark A. Alexander
发明人： Peter H. Alfke , Mark A. Alexander
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361
摘要： An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.
摘要翻译： IC使用数据源和数据目的地之间的可调谐互连驱动器来选择性地减慢（“调整”）数据信号。 沿相对较短路径发送的数据被去调整，以减少同步切换事件期间的电源噪声。 在一些实施例中，可调谐互连驱动器相对于未延迟的信号路径延迟数据传输，在其他实施例中，可选择性地减少可调谐互连驱动器的转换速率。
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10.发明授权公开(公告)号：US07138815B1
公开(公告)日：2006-11-21
申请号：US10746587
申请日：2003-12-24
申请人： Mark A. Alexander , Sean A. Koontz
发明人： Mark A. Alexander , Sean A. Koontz
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/2853 , G01R31/3004 , G01R31/31721
摘要： A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.
摘要翻译： 封装的半导体器件在半导体管芯内产生的电流不连续性中使用内置的自我测试来表征半导体管芯内的点之间的电压。 操作半导体管芯以产生电流不连续性或几个连续的电流不连续性，并且使用片上ADC测量电压。 测量半导体管芯内的电压，而不是在外部测试点进行测量，可以更准确地预测器件的工作。 使用多路复用器，多个ADC或通过重新配置FPGA来测量多个测试点。 通过转换在电流不连续期间测量的通过半导体管芯的电压和电流来获得连接到半导体管芯的较大配电系统的阻抗与频率信息。
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