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公开(公告)号：US07127664B2
公开(公告)日：2006-10-24
申请号：US09908003
申请日：2001-07-18
IPC分类号： H03M13/00
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/3905 , H03M13/3927 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6502 , H03M13/6505 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6566 , H04L1/0052 , H04L1/0054 , H04L1/0055
摘要： The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.
摘要翻译： 本发明公开了一种用于在一种架构中执行卷积解码和turbo解码的单一统一解码器。 统一解码器可以动态分区，以不同吞吐率对不同数量的数据流执行所需的解码操作。 它还支持语音（卷积解码）和数据（turbo解码）流的同时解码。 本发明构成了可解码TDMA，IS-95，GSM，GPRS，EDGE，UMTS和CDMA2000的所有标准的解码器的基础。 处理器堆叠在一起并互连，使得它们可以单独执行单独的解码器或与单个高速解码器协调。 统一的解码器架构可以同时支持多个数据流和多个语音流。 此外，解码器可以根据需要被动态分割，以解码用于不同标准的语音流。
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公开(公告)号：US06865710B2
公开(公告)日：2005-03-08
申请号：US09908000
申请日：2001-07-18
IPC分类号： G06F11/10 , G06F17/10 , G06F17/14 , H03M13/23 , H03M13/27 , H03M13/29 , H03M13/39 , H03M13/41 , H04L1/00 , H03M13/00
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/3905 , H03M13/3927 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6502 , H03M13/6505 , H03M13/6508 , H03M13/6511 , H03M13/6516 , H03M13/6566 , H04L1/0052 , H04L1/0054 , H04L1/0055
摘要： The present invention discloses a butterfly processor capable of performing convolutional decoding and LogMAP decoding in telecommunications systems. First and second add-compare-select modules are provided for receiving input path metrics. A branch metric calculator is also provided for receiving input data and extrinsic data. The branch metric calculator generates output branch metrics to each of the first and second add-compare-select modules. Each of the add-compare-select modules includes a log-sum correction means coupled to compare and select components. A controllable switch selectively couples outputs of the select components and the log-sum corrections means to enable either one of convolutional or LogMAP decoding.
摘要翻译： 本发明公开了一种能够在电信系统中执行卷积解码和LogMAP解码的蝶形处理器。 提供第一和第二加法比较选择模块用于接收输入路径度量。 还提供分支度量计算器用于接收输入数据和外部数据。 分支度量计算器向第一和第二加法比较选择模块中的每一个生成输出分支度量。 每个加法比较选择模块包括耦合以比较和选择部件的对数和校正装置。 可控开关选择性地耦合选择部件和对数和校正装置的输出，以实现卷积或LogMAP解码中的任一个。
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3.发明授权Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder 失效改进的分支度量计算器，以减少交织器存储器并提高定点turbo解码器的性能公开(公告)号：US08196006B2
公开(公告)日：2012-06-05
申请号：US12323558
申请日：2008-11-26
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/2771 , H03M13/3927
摘要： A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.
摘要翻译： 计算α，β和γ（分支度量）值的turbo解码器不会使分支度量标准化，而是在将它们写入交织存储器之前将归一化因子应用于新计算的外在值，导致使用比现有涡轮机更少的存储器 解码器 当从交织存储器中读取二进制时，应用补偿因子。 伽马计算中不存在归一化不仅节约了存储器，而且增强了解码器的灵敏度。
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公开(公告)号：US07085791B2
公开(公告)日：2006-08-01
申请号：US10366383
申请日：2003-02-14
IPC分类号： G06F1/02
CPC分类号： G06F7/586
摘要： In the method of generating a pseudo random number, pseudo random numbers equal to pseudo random numbers generated from a pseudo random number generation function indexed by orders of two are stored. Then, a pseudo random number is generated based on the stored pseudo random numbers.
摘要翻译： 在生成伪随机数的方法中，存储等于由二阶索引的伪随机数生成函数生成的伪随机数的伪随机数。 然后，基于存储的伪随机数生成伪随机数。
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5.发明授权公开(公告)号：US07020214B2
公开(公告)日：2006-03-28
申请号：US09908188
申请日：2001-07-18
IPC分类号： H04L23/02
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/3927 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169 , H03M13/6502 , H03M13/6505 , H03M13/6508 , H03M13/6511 , H03M13/6516 , H03M13/6566 , H04L1/0052 , H04L1/0054 , H04L1/0055
摘要： An apparatus and a method for calculating in-place pat metric addressing far a trellis processing arrangement are provided. An arrangement of cascaded multiplexers and stores receives a known input sequence of path metrics. The input sequence of path metrics is manipulated such that certain of the path metrics are delayed in the stores by a clock cycle, whilst the remaining path metrics are presented to the cascaded banks of multiplexers. In this manner, the input sequence of path metrics is continuously processed to produce a desired output sequence of path metrics. Advantageously, embodiments of the apparatus and method may be practiced on either a forward trellis or a reverse trellis.
摘要翻译： 提供了一种用于计算远处网格处理布置的就地拍摄度量的装置和方法。 级联多路复用器和存储器的布置接收路径度量的已知输入序列。 操纵路径度量的输入序列，使得某些路径量度在存储器中被延迟时钟周期，而其余的路径量度被提供给级联的多路复用器组。 以这种方式，路径度量的输入序列被连续处理以产生所需的路径度量输出序列。 有利地，装置和方法的实施例可以在前向网格或反向网格上实施。
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公开(公告)号：US08135383B2
公开(公告)日：2012-03-13
申请号：US11830399
申请日：2007-07-30
IPC分类号： H04M1/66
摘要： A method includes storing at least one user datum received from a user in a secure storage portion of a memory within a mobile communication device. Authentication information is received into the mobile communication device. The at least one user datum is transmitted from the mobile communication device to a recipient in response to entry of the authentication information, while preventing the user of the mobile communication device from reading the at least one user datum.
摘要翻译： 一种方法包括将从用户接收的至少一个用户数据存储在移动通信设备内的存储器的安全存储部分中。 验证信息被接收到移动通信设备中。 响应于认证信息的输入，至少一个用户数据从移动通信设备发送到接收者，同时防止移动通信设备的用户读取至少一个用户数据。
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7.发明授权Unified serial/parallel concatenated convolutional code decoder architecture and method 有权统一串行/并行级联卷积码解码器架构与方法公开(公告)号：US07200798B2
公开(公告)日：2007-04-03
申请号：US10608831
申请日：2003-06-26
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/2972 , H03M13/2978 , H03M13/395 , H03M13/6511
摘要： A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.
摘要翻译： 具有两种操作模式的turbo解码器根据N状态的基数K格网解码接收到的信息，其中N和K是等于1或更大的整数。 turbo解码器使用在线寻址技术，其允许其在第一操作模式中作为串行卷积码解码器操作，并且在第二操作模式中使用并行卷积码解码器。 解码器使用在线寻址技术，允许它在处理接收到的信息时使用相同的存储器块来存储和检索格状态。 turbo解码器也可以按照N状态的基数K网格进行操作，其中N是等于2或更大的整数，K是等于4或更大的整数。
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8.发明授权Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder 失效改进的分支度量计算器，以减少交织器存储器并提高定点turbo解码器的性能公开(公告)号：US07464316B2
公开(公告)日：2008-12-09
申请号：US11212186
申请日：2005-08-26
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/2771 , H03M13/3927
摘要： A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.
摘要翻译： 计算α，β和γ（分支度量）值的turbo解码器不会使分支度量标准化，而是在将它们写入交织存储器之前将归一化因子应用于新计算的外在值，导致使用比现有涡轮机更少的存储器 解码器 当从交织存储器中读取二进制时，应用补偿因子。 伽马计算中不存在归一化不仅节约了存储器，而且增强了解码器的灵敏度。
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公开(公告)号：US06851039B2
公开(公告)日：2005-02-01
申请号：US10259600
申请日：2002-09-30
CPC分类号： H03M13/6502 , G06F7/722 , G11B20/00195 , H03M13/2714 , H03M13/2764 , H03M13/2767 , H03M13/2957
摘要： In the method of generating an interleaved address, each 2^i mod (p−1) value for i=0 to x−1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x is greater than one. An inter-row sequence number is multiplied with a column index number to obtain a binary product. Both the inter-row sequence number and the column index number are for the block size K and the prime number p. Then, each binary component of the binary product is multiplied with a respective one of the stored 2^i mod (p−1) values to obtain a plurality of intermediate mod value. An intra-row permutation address is generated based on the plurality of intermediate mod values, and an interleaved address is generated based on the intra-row permutation address.
摘要翻译： 在产生交织地址的方法中，存储i = 0至x-1的每个2 ^ i mod（p-1）值。 这里，p是取决于被处理的数据块的块大小K并且x大于1的素数。 将行间序列号乘以列索引号以获得二进制乘积。 行间序列号和列索引号都用于块大小K和素数p。 然后，将二进制积的每个二进制分量与存储的2 ^ i mod（p-1）值中的相应一个相乘以获得多个中间mod值。 基于多个中间mod值生成行内置换地址，并且基于行内置换地址生成交织地址。
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10.发明授权Method and apparatus for block and rate independent decoding of LDPC codes 失效用于LDPC码的块和速率独立解码的方法和装置公开(公告)号：US07607065B2
公开(公告)日：2009-10-20
申请号：US11191158
申请日：2005-07-27
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1111 , H03M13/6516
摘要： Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.
摘要翻译： 提供了用于LDPC码的块速率独立解码的方法和装置。 所公开的LDPC解码器支持多个码块长度和码率，以及可变奇偶校验矩阵。 所公开的LDPC解码器对基于具有多个子矩阵的奇偶校验矩阵的LDPC码进行解码，其中多个子矩阵中的每一行和列具有单个条目。 每个子矩阵具有至少一个相关联的Phi节点，其中每个Phi节点包括具有多个存储器元件的存储器件，其中一个或多个存储器元件可被选择性地禁用。 Phi节点可以被选择性地禁用，例如在运行时。 Phi节点可选地还包括多路复用器以提供可变奇偶校验矩阵。
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