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    Overlay process for fabricating a semiconductor device
    2.
    发明授权
    Overlay process for fabricating a semiconductor device 失效
    用于制造半导体器件的叠层工艺

    公开(公告)号：US06228705B1

    公开(公告)日：2001-05-08

    申请号：US09243221

    申请日：1999-02-03

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    IPC分类号： H01L218242

    CPC分类号： H01L23/544 ,  H01L27/10861 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for fabricating a semiconductor device. In an exemplary embodiment, the process includes the following steps. The process initially defines a first registration mark associated with a first mask level of the semiconductor device and a second registration mark associated with a second mask level of the semiconductor device. The process then defines a third registration mark associated with a third mask level of the semiconductor device based on the first and second registration marks. Finally, the process aligns the third mask level along a first axis with respect to the first registration mark, and aligns the third mask level along a second axis with respect to the second registration mark. According to various aspects of the invention, the semiconductor fabrication process is used to fabricate DRAM trench cells, or any other type of semiconductor device whose fabrication requires tight overlay alignment between the various levels of the device.

    摘要翻译： 一种制造半导体器件的工艺。 在示例性实施例中，该过程包括以下步骤。 该过程最初定义与半导体器件的第一掩模级相关联的第一对准标记和与半导体器件的第二掩模级相关联的第二对准标记。 然后，该过程基于第一和第二对准标记来定义与半导体器件的第三掩模级相关联的第三对准标记。 最后，该过程相对于第一对准标记沿着第一轴对准第三掩模级，并且使第三掩模级别相对于第二对准标记沿着第二轴线对齐。 根据本发明的各个方面，半导体制造工艺用于制造DRAM沟槽单元或其制造需要在器件的各个级别之间紧密重叠对准的任何其它类型的半导体器件。

    Patterned recess formation using acid diffusion
    3.
    发明授权
    Patterned recess formation using acid diffusion 失效
    使用酸扩散形成图形凹陷

    公开(公告)号：US06221680B1

    公开(公告)日：2001-04-24

    申请号：US09127132

    申请日：1998-07-31

    申请人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

    发明人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

    IPC分类号： H01L2100

    CPC分类号： H01L21/0273 ,  G03F7/094 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/312 ,  H01L21/31625 ,  H01L27/10861

    摘要： The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.

    摘要翻译： 本发明涉及一种用于在半导体结构（即DRAM沟槽电容器）的预先凹入的区域中提供图案化的凹陷形成的方法，其使用酸扩散来选择性地激活填充在凹陷区域内的一些但不是全部的酸敏感材料 的这种结构。 通过采用本发明的方法，可以同时在所有先前的凹陷区域内提供相同水平的凹入的酸敏感材料，同时将所有先前凹陷的区域都凹进，将一些先前凹陷的区域凹入到期望的水平位置 结构的其他部分不能被加工，或者使先前凹陷的区域凹陷以包含不同水平的酸敏感材料。

    Method for a controlled bottle trench for a dram storage node
    4.
    发明授权
    Method for a controlled bottle trench for a dram storage node 失效
    一种用于剧烈储存节点的受控瓶沟的方法

    公开(公告)号：US06190988B1

    公开(公告)日：2001-02-20

    申请号：US09086174

    申请日：1998-05-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

    摘要翻译： 在受控蚀刻工艺中形成具有掩埋板的瓶形沟槽电容器。 通过使用这些层作为掩模蚀刻来自分层衬底的深沟槽，并用保护的氧化物和氮化物层覆盖衬底的侧壁来制造瓶形。 在侧壁被覆盖的情况下，然后恢复深沟槽蚀刻，并且形成在侧壁的保护层下方的下沟槽部分。 通过在深沟槽区域的下部扩散第一掺杂剂，使用侧壁保护层作为掩模，建立了在由第一掺杂剂建立的p / n结处的湿蚀刻工艺的蚀刻停止。 下沟槽部分的宽度由扩散的时间和温度来调节。 去除掺杂材料并向下沟槽部分施加第二掺杂剂在沟槽之间建立连续的掩埋板区域。 通过向沟槽施加绝缘层并填充导体来形成电容器。

    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
    6.
    发明申请
    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
    多层和单层平面定向半导体基板

    公开(公告)号：US20080099844A1

    公开(公告)日：2008-05-01

    申请号：US11969320

    申请日：2008-01-04

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    IPC分类号： H01L29/786

    CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

    摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

    摘要翻译： 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。

    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION
    7.
    发明申请
    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
    通过选择性沉积的微电子结构

    公开(公告)号：US20080001225A1

    公开(公告)日：2008-01-03

    申请号：US11307294

    申请日：2006-01-31

    申请人： Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

    发明人： Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

    摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

    摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
    9.
    发明申请
    WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES 失效
    用于CMOS器件的绝缘隔离（WIT）

    公开(公告)号：US20070241408A1

    公开(公告)日：2007-10-18

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    Layout and process to contact sub-lithographic structures
    10.
    发明申请
    Layout and process to contact sub-lithographic structures 有权
    接触亚光刻结构的布局和工艺

    公开(公告)号：US20070215874A1

    公开(公告)日：2007-09-20

    申请号：US11378492

    申请日：2006-03-17

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

    IPC分类号： H01L23/58

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

    摘要翻译： 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。