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    Method for a controlled bottle trench for a dram storage node
    1.
    发明授权
    Method for a controlled bottle trench for a dram storage node 失效
    一种用于剧烈储存节点的受控瓶沟的方法

    公开(公告)号：US06190988B1

    公开(公告)日：2001-02-20

    申请号：US09086174

    申请日：1998-05-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

    摘要翻译： 在受控蚀刻工艺中形成具有掩埋板的瓶形沟槽电容器。 通过使用这些层作为掩模蚀刻来自分层衬底的深沟槽，并用保护的氧化物和氮化物层覆盖衬底的侧壁来制造瓶形。 在侧壁被覆盖的情况下，然后恢复深沟槽蚀刻，并且形成在侧壁的保护层下方的下沟槽部分。 通过在深沟槽区域的下部扩散第一掺杂剂，使用侧壁保护层作为掩模，建立了在由第一掺杂剂建立的p / n结处的湿蚀刻工艺的蚀刻停止。 下沟槽部分的宽度由扩散的时间和温度来调节。 去除掺杂材料并向下沟槽部分施加第二掺杂剂在沟槽之间建立连续的掩埋板区域。 通过向沟槽施加绝缘层并填充导体来形成电容器。

    Overlay process for fabricating a semiconductor device
    2.
    发明授权
    Overlay process for fabricating a semiconductor device 失效
    用于制造半导体器件的叠层工艺

    公开(公告)号：US06228705B1

    公开(公告)日：2001-05-08

    申请号：US09243221

    申请日：1999-02-03

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    IPC分类号： H01L218242

    CPC分类号： H01L23/544 ,  H01L27/10861 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for fabricating a semiconductor device. In an exemplary embodiment, the process includes the following steps. The process initially defines a first registration mark associated with a first mask level of the semiconductor device and a second registration mark associated with a second mask level of the semiconductor device. The process then defines a third registration mark associated with a third mask level of the semiconductor device based on the first and second registration marks. Finally, the process aligns the third mask level along a first axis with respect to the first registration mark, and aligns the third mask level along a second axis with respect to the second registration mark. According to various aspects of the invention, the semiconductor fabrication process is used to fabricate DRAM trench cells, or any other type of semiconductor device whose fabrication requires tight overlay alignment between the various levels of the device.

    摘要翻译： 一种制造半导体器件的工艺。 在示例性实施例中，该过程包括以下步骤。 该过程最初定义与半导体器件的第一掩模级相关联的第一对准标记和与半导体器件的第二掩模级相关联的第二对准标记。 然后，该过程基于第一和第二对准标记来定义与半导体器件的第三掩模级相关联的第三对准标记。 最后，该过程相对于第一对准标记沿着第一轴对准第三掩模级，并且使第三掩模级别相对于第二对准标记沿着第二轴线对齐。 根据本发明的各个方面，半导体制造工艺用于制造DRAM沟槽单元或其制造需要在器件的各个级别之间紧密重叠对准的任何其它类型的半导体器件。

    Increased capacitance trench capacitor
    3.
    发明授权
    Increased capacitance trench capacitor 失效
    增加电容沟槽电容

    公开(公告)号：US06620675B2

    公开(公告)日：2003-09-16

    申请号：US09682607

    申请日：2001-09-26

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  William H. Ma

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/87 ,  H01L29/945 ,  Y10S438/964

    摘要： Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.

    摘要翻译： 公开了通过增加侧壁面积来增加沟槽电容器的电容的方法，包括：在硅衬底中形成沟槽，所述沟槽具有侧壁; 在沟槽的侧壁上形成岛; 并使用岛作为掩模将凹坑蚀刻到侧壁中。 通过在凹坑和侧壁上形成节点绝缘体来完成电容器; 以及用沟槽导体填充所述沟槽。

    Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer
    7.
    发明授权
    Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer 失效
    使用锗氧化物牺牲层将掺杂剂引入半导体器件的方法

    公开(公告)号：US06333245B1

    公开(公告)日：2001-12-25

    申请号：US09469137

    申请日：1999-12-21

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Donald W. Rakowski

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Donald W. Rakowski

    IPC分类号： H01L2122

    CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842

    摘要： A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.

    摘要翻译： 公开了一种使用掺杂的氧化锗将掺杂剂引入半导体器件的方法。 该方法包括使用快速热退火（RTA）或炉退火来从半导体衬底上的掺杂的锗氧化物牺牲层将掺杂剂扩散到衬底中。 退火之后将掺杂剂扩散到衬底中，使用水去除锗氧化物牺牲层，从而避免在栅极或标准器件隔离结构中去除二氧化硅（SiO 2），这可能导致器件故障。 N +和p +源极和漏极可以在半导体衬底中的适当的阱中使用单一退火形成，并且不需要限定第一掺杂牺牲层的不止一个区域。 或者，在将第二掺杂剂引入到氧化锗牺牲层中之前的退火给出较慢的扩散离子，例如砷开始。

    Method of manufacturing dual gate logic devices
    10.
    发明授权
    Method of manufacturing dual gate logic devices 失效
    制造双门逻辑器件的方法

    公开(公告)号：US06596597B2

    公开(公告)日：2003-07-22

    申请号：US09879590

    申请日：2001-06-12

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    IPC分类号： H01L21336

    CPC分类号： H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

    摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

    摘要翻译： 本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在电介质壳体中而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。