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    Overlay process for fabricating a semiconductor device
    3.
    发明授权
    Overlay process for fabricating a semiconductor device 失效
    用于制造半导体器件的叠层工艺

    公开(公告)号：US06228705B1

    公开(公告)日：2001-05-08

    申请号：US09243221

    申请日：1999-02-03

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma

    IPC分类号： H01L218242

    CPC分类号： H01L23/544 ,  H01L27/10861 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for fabricating a semiconductor device. In an exemplary embodiment, the process includes the following steps. The process initially defines a first registration mark associated with a first mask level of the semiconductor device and a second registration mark associated with a second mask level of the semiconductor device. The process then defines a third registration mark associated with a third mask level of the semiconductor device based on the first and second registration marks. Finally, the process aligns the third mask level along a first axis with respect to the first registration mark, and aligns the third mask level along a second axis with respect to the second registration mark. According to various aspects of the invention, the semiconductor fabrication process is used to fabricate DRAM trench cells, or any other type of semiconductor device whose fabrication requires tight overlay alignment between the various levels of the device.

    摘要翻译： 一种制造半导体器件的工艺。 在示例性实施例中，该过程包括以下步骤。 该过程最初定义与半导体器件的第一掩模级相关联的第一对准标记和与半导体器件的第二掩模级相关联的第二对准标记。 然后，该过程基于第一和第二对准标记来定义与半导体器件的第三掩模级相关联的第三对准标记。 最后，该过程相对于第一对准标记沿着第一轴对准第三掩模级，并且使第三掩模级别相对于第二对准标记沿着第二轴线对齐。 根据本发明的各个方面，半导体制造工艺用于制造DRAM沟槽单元或其制造需要在器件的各个级别之间紧密重叠对准的任何其它类型的半导体器件。

    Patterned recess formation using acid diffusion
    4.
    发明授权
    Patterned recess formation using acid diffusion 失效
    使用酸扩散形成图形凹陷

    公开(公告)号：US06221680B1

    公开(公告)日：2001-04-24

    申请号：US09127132

    申请日：1998-07-31

    申请人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

    发明人： Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Toshiharu Furukawa

    IPC分类号： H01L2100

    CPC分类号： H01L21/0273 ,  G03F7/094 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/312 ,  H01L21/31625 ,  H01L27/10861

    摘要： The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.

    摘要翻译： 本发明涉及一种用于在半导体结构（即DRAM沟槽电容器）的预先凹入的区域中提供图案化的凹陷形成的方法，其使用酸扩散来选择性地激活填充在凹陷区域内的一些但不是全部的酸敏感材料 的这种结构。 通过采用本发明的方法，可以同时在所有先前的凹陷区域内提供相同水平的凹入的酸敏感材料，同时将所有先前凹陷的区域都凹进，将一些先前凹陷的区域凹入到期望的水平位置 结构的其他部分不能被加工，或者使先前凹陷的区域凹陷以包含不同水平的酸敏感材料。

    Method for a controlled bottle trench for a dram storage node
    5.
    发明授权
    Method for a controlled bottle trench for a dram storage node 失效
    一种用于剧烈储存节点的受控瓶沟的方法

    公开(公告)号：US06190988B1

    公开(公告)日：2001-02-20

    申请号：US09086174

    申请日：1998-05-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  William H. Ma ,  James M. Never

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

    摘要翻译： 在受控蚀刻工艺中形成具有掩埋板的瓶形沟槽电容器。 通过使用这些层作为掩模蚀刻来自分层衬底的深沟槽，并用保护的氧化物和氮化物层覆盖衬底的侧壁来制造瓶形。 在侧壁被覆盖的情况下，然后恢复深沟槽蚀刻，并且形成在侧壁的保护层下方的下沟槽部分。 通过在深沟槽区域的下部扩散第一掺杂剂，使用侧壁保护层作为掩模，建立了在由第一掺杂剂建立的p / n结处的湿蚀刻工艺的蚀刻停止。 下沟槽部分的宽度由扩散的时间和温度来调节。 去除掺杂材料并向下沟槽部分施加第二掺杂剂在沟槽之间建立连续的掩埋板区域。 通过向沟槽施加绝缘层并填充导体来形成电容器。

    Implantation of gate regions in semiconductor device fabrication
    8.
    发明授权
    Implantation of gate regions in semiconductor device fabrication 失效
    在半导体器件制造中植入栅极区域

    公开(公告)号：US07557023B2

    公开(公告)日：2009-07-07

    申请号：US11532189

    申请日：2006-09-15

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

    摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

    摘要翻译： 半导体制造方法。 该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。 栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。 半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。 接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。 接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。