公开(公告)号：US6013546A

公开(公告)日：2000-01-11

申请号：US994084

申请日：1997-12-19

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Jack C. Lee

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Jack C. Lee

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L21/8249

CPC分类号： H01L21/26506 ,  H01L21/2652 ,  H01L21/823814

摘要： A semiconductor device is formed which includes a shallow PMOS active region containing a heavy atom p-type dopant material. In an exemplary process for making a PMOS device or portion of a device, at least one PMOS gate electrode is formed over a PMOS device region of a substrate. A PMOS spacer is formed on a sidewall of a PMOS gate electrode. An amorphizing dopant material is selectively implanted into a PMOS active region using the PMOS spacer as a mask. A heavy atom p-type dopant material is selectively implanted into the PMOS active region using the PMOS spacer as a mask. The order of implantation of the amorphizing dopant material and the heavy atom p-type dopant material may be reversed.

摘要翻译： 形成包括含有重原子p型掺杂剂材料的浅PMOS有源区的半导体器件。 在用于制造PMOS器件或器件的一部分的示例性工艺中，在衬底的PMOS器件区域上形成至少一个PMOS栅电极。 PMOS间隔物形成在PMOS栅电极的侧壁上。 使用PMOS间隔物作为掩模，将非晶化掺杂剂材料选择性地注入到PMOS有源区中。 使用PMOS间隔物作为掩模，将重原子p型掺杂剂材料选择性地注入到PMOS有源区中。 非晶化掺杂剂材料和重原子p型掺杂剂材料的注入顺序可以颠倒。

公开(公告)号：US6057584A

公开(公告)日：2000-05-02

申请号：US994302

申请日：1997-12-19

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583 ,  H01L21/2822 ,  H01L21/28229

摘要： A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.

摘要翻译： 具有栅绝缘三层的半导体器件包括衬底，设置在衬底上的含氮层，设置在含氮层上的第一介电层，设置在第一介电层上的第二电介质层和栅电极 设置在第二电介质层上。 使用介电常数为4〜100的氧化物形成第一和第二电介质层中的一个，并且使用介电常数介于10〜10000的氧化物形成第一和第二电介质层中的另一个。

公开(公告)号：US6146934A

公开(公告)日：2000-11-14

申请号：US994818

申请日：1997-12-19

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Jack C. Lee

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Jack C. Lee

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/7835 ,  H01L29/6656

摘要： A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.

摘要翻译： PMOS或CMOS器件包括具有浅重原子p型植入物的有源区域。 PMOS器件具有衬底，设置在衬底上的至少一个栅电极以及邻近栅电极设置的第一和第二掺杂有源区。 第一有源区具有比第二有源区高的p型重原子掺杂剂材料的浓度。 在形成PMOS器件的一种方法中，在栅电极的侧壁上形成间隔物。 使用间隔物作为掩模，将第一p型掺杂剂材料选择性地注入到与栅电极相邻的有源区域中。 然后去除一个间隔物的一部分以形成更薄的间隔物，并且使用较薄的间隔物作为掩模，将第二p型掺杂剂材料选择性地注入到第一个有源区中。 第二种p型掺杂剂材料是重原子物质。

公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

公开(公告)号：US06531364B1

公开(公告)日：2003-03-11

申请号：US09129703

申请日：1998-08-05

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.

摘要翻译： 提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。 然后可以将牺牲多晶硅层还原成所需的厚度。 牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。 作为选择，可以加热牺牲多晶硅层使其重结晶。 牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。 多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

公开(公告)号：US06303962B1

公开(公告)日：2001-10-16

申请号：US09227512

申请日：1999-01-06

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： A01L2701

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/78675

摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.

摘要翻译： 在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。 晶体管的栅极也可以由诸如金属的低电阻材料形成。 晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。 为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。 源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。 位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。 随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。 所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

公开(公告)号：US06255698B1

公开(公告)日：2001-07-03

申请号：US09301263

申请日：1999-04-28

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).

摘要翻译： 提供并形成了包含用于n沟道和p沟道晶体管的单独优化的栅极结构的集成电路。 用于n沟道和p沟道晶体管的原始栅极结构在半导体衬底的适当掺杂的有源区上被图案化。 在半导体衬底上形成与原始栅极结构的上表面相同的高度水平面的保护电介质，使得只有栅极结构的上表面露出。 掩模层用于覆盖p沟道或n沟道晶体管的栅极结构。 去除未覆盖的栅极结构，在保护电介质内形成沟槽，代替每个去除的栅极结构。 沟槽用新的栅极结构重新填充，该栅极结构优选地适合于适当的晶体管类型（n沟道或p沟道）的操作。

公开(公告)号：US06239467B1

公开(公告)日：2001-05-29

申请号：US09183616

申请日：1998-10-30

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Anthony Toprac

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Anthony Toprac

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L22/20 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

摘要： A semiconductor device having a controlled drive current strength is produced by varying spacer width to accommodate any variation in gate electrode length from a desired value. After formation of the gate electrode on a substrate, the length is measured and compared to a desired value. Based on any differences between the measured and desired values, the width of spacer is determined in order to counteract the variation in gate electrode length. This results in maintaining the desired channel length after dopant implanting, to provide the desired drive current strength. The present process permits close control over the drive current strength of semiconductor devices and also decreased variation within and between lots and corresponding increases in productivity.

摘要翻译： 具有受控的驱动电流强度的半导体器件通过改变间隔物宽度来产生，以适应栅电极长度与期望值的任何变化。 在基板上形成栅电极之后，测量长度并将其与期望值进行比较。 基于测量值和期望值之间的任何差异，确定间隔物的宽度以抵消栅电极长度的变化。 这导致在掺杂剂注入之后保持期望的沟道长度，以提供期望的驱动电流强度。 本方法允许对半导体器件的驱动电流强度进行密切控制，并且还可以减少批次之间和批量之间的变化，并且相应地提高生产率。

公开(公告)号：US06225646B1

公开(公告)日：2001-05-01

申请号：US09483557

申请日：2000-01-14

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L3300

CPC分类号： H01L27/0688 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit is presented. The integrated circuit may include a memory cell formed above an insulating base. The insulating base may either be arranged above a substrate or serve as a substrate itself. A transistor may be arranged above the memory cell. The transistor is preferably dielectrically isolated from the memory cell. In a preferred embodiment, a segmented substrate is arranged between the memory cell and transistor. The segmented substrate preferably includes a first conductive substrate layer arranged above and dielectrically spaced from the memory cell. A second conductive substrate layer may be formed above the first conductive substrate layer. The transistor may be arranged upon and within the second conductive substrate layer. Preferably, the segmented substrate further includes an intersubstrate dielectric layer interposed between the second conductive substrate layer and the first conductive substrate layer. The intersubstrate dielectric layer preferably serves to insulate the first conductive substrate layer from the second conductive substrate layer. An integrated circuit so configured may be fabricated with greater device density at reduced cost.

摘要翻译： 介绍了一个集成电路。 集成电路可以包括形成在绝缘基底上方的存储单元。 绝缘基底可以布置在基底之上或用作基底本身。 晶体管可以布置在存储器单元的上方。 晶体管优选地与存储单元介电隔离。 在优选实施例中，分段衬底被布置在存储器单元和晶体管之间。 分段基板优选​​地包括布置在存储单元上方并与该存储单元间隔开的第一导电基板层。 第二导电衬底层可以形成在第一导电衬底层的上方。 晶体管可以布置在第二导电衬底层之上和之内。 优选地，分段基板还包括插入在第二导电基板层和第一导电基板层之间的基板间电介质层。 衬底间电介质层优选用于使第一导电衬底层与第二导电衬底层绝缘。 如此构造的集成电路可以以更低的成本制造具有更大的器件密度。

公开(公告)号：US06225188B1

公开(公告)日：2001-05-01

申请号：US09524447

申请日：2000-03-14

申请人： Derick J. Wristers ,  H. Jim Fulford ,  Mark I. Gardner

发明人： Derick J. Wristers ,  H. Jim Fulford ,  Mark I. Gardner

IPC分类号： H01L21265

CPC分类号： H01L21/76237

摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative proximal to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

摘要翻译： 提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。 氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。 然后在半导体衬底的上表面上形成栅介质层。 在半导体衬底的近端部分存在含氧物质增加了部分相对于离开隔离结构远端的部分氧化速率的氧化速率。 以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。 与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。