公开(公告)号：US06934190B1

公开(公告)日：2005-08-23

申请号：US10863933

申请日：2004-06-09

申请人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

发明人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

摘要翻译： 提供了包括具有一定范围值的编程的双位存储器件的操作方法。 本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。 该范围与存储器件内的各个双位存储单元的通道长度有关。 为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。 此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。 然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

公开(公告)号：US20060291282A1

公开(公告)日：2006-12-28

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

公开(公告)号：US07120063B1

公开(公告)日：2006-10-10

申请号：US10841850

申请日：2004-05-07

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US07215577B2

公开(公告)日：2007-05-08

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/78

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US06834012B1

公开(公告)日：2004-12-21

申请号：US10863673

申请日：2004-06-08

申请人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

发明人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.

摘要翻译： 提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。 本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。 通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。

公开(公告)号：US08508999B2

公开(公告)日：2013-08-13

申请号：US13451656

申请日：2012-04-20

申请人： Zengtao Liu ,  Graham Wolstenholme

发明人： Zengtao Liu ,  Graham Wolstenholme

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

摘要： A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.

摘要翻译： 垂直NAND结构包括具有至少两个功能模式的一个或多个中串式装置。 在第一模式中，一个或多个中串式装置将NAND存储器单元堆叠的主体耦合到衬底以进行擦除操作。 在第二模式中，一个或多个中串装置将第一堆NAND存储器单元的主体耦合到第二堆存储器NAND存储器单元的主体，允许两个堆作为单个NAND串用于读取和 编程操作。

公开(公告)号：US20120012921A1

公开(公告)日：2012-01-19

申请号：US12836853

申请日：2010-07-15

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/088 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

公开(公告)号：US07259984B2

公开(公告)日：2007-08-21

申请号：US10718662

申请日：2003-11-24

申请人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

发明人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

IPC分类号： G11C11/34

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06

摘要： Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 106s, and provide 2-bit-per-cell storage capability.

摘要翻译： 金属纳米晶体存储器被制造成包括比半导体纳米晶体器件可用的更高密度状态，更强的与沟道的耦合以及更好的尺寸可扩展性。 通过沉积在栅极氧化物顶部的超薄金属膜的快速热退火的自组装纳米晶体形成工艺与NMOSFET集成以制造这种器件。 具有在FN隧穿状态下工作的Au，Ag和Pt纳米晶体的器件以热载流子注入作为编程机制，证明保留时间高达10 6，并提供2位/ 细胞储存能力。

公开(公告)号：US20060216922A1

公开(公告)日：2006-09-28

申请号：US11407429

申请日：2006-04-20

申请人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US08559231B2

公开(公告)日：2013-10-15

申请号：US13043005

申请日：2011-03-08

申请人： Akira Goda ,  Zengtao Liu

发明人： Akira Goda ,  Zengtao Liu

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/025 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

摘要： One method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers). In one embodiment, the target threshold voltage range can be shifted lower for a slower programming layer. This might be accomplished by biasing the bit lines of slower programming layers with higher bit line voltages as compared to bit line voltages of faster programming layers.

摘要翻译： 用于感测的一种方法包括响应于该特定层的编程速率（例如，相对于其它层）改变特定层的感测条件。 在一个实施例中，对于较慢的编程层，目标阈值电压范围可以更低。 与较快编程层的位线电压相比，可以通过将较慢编程层的位线与较高位线电压相比较来实现。