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公开(公告)号：US07398355B1
公开(公告)日：2008-07-08
申请号：US11195093
申请日：2005-08-01
申请人： Mark S. Moir , Marc Tremblay , Shailender Chaudhry
发明人： Mark S. Moir , Marc Tremblay , Shailender Chaudhry
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/528 , G06F12/0815 , G06F12/0862
摘要： One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or more critical sections which are protected by locks. Next, the system modifies the program so that the critical sections which are protected by locks are executed transactionally without acquiring locks associated with the critical sections. More specifically, the program is modified so that: (1) during transactional execution of a critical section, the program first determines if a lock associated with the critical section is held by another process and if so aborts the transactional execution; (2) if the transactional execution of the critical section completes without encountering an interfering data access from another process, the program commits changes made during the transactional execution and optionally resumes normal non-transactional execution of the program past the critical section; and (3) if an interfering data access from another process is encountered during transactional execution of the critical section, the program discards changes made during the transactional execution, and attempts to re-execute the critical section zero or more times.
摘要翻译： 本发明的一个实施例提供一种通过事务执行关键部分来避免锁定的系统。 在操作期间，系统接收包括被锁保护的一个或多个关键部分的程序。 接下来，系统修改程序，使得受锁保护的关键部分在事务上执行，而不获取与关键部分相关联的锁定。 更具体地说，修改程序使得：（1）在关键部分的事务执行期间，程序首先确定与关键部分相关联的锁定是否被另一进程保持，如果是这样，中止事务执行; （2）如果关键部分的事务执行完成而没有遇到来自另一进程的干扰数据访问，则该程序提交在事务执行期间所做的更改，并且可选地恢复通过关键部分的程序的正常非事务性执行; 和（3）如果在关键部分的事务执行期间遇到来自其他进程的干扰数据访问，则程序将丢弃事务执行期间所做的更改，并尝试重新执行关键部分零次或多次。
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2.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07389383B2
公开(公告)日：2008-06-17
申请号：US11399049
申请日：2006-04-06
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
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3.发明授权Method and apparatus for releasing memory locations during transactional execution 有权在事务执行期间释放内存位置的方法和装置公开(公告)号：US07206903B1
公开(公告)日：2007-04-17
申请号：US10895519
申请日：2004-07-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.
摘要翻译： 本发明的一个实施例提供了一种用于将存储器位置从事务程序执行释放的系统。 该系统通过在事务性程序执行期间执行指令序列来操作，其中监视涉及事务性程序执行的存储器位置以检测来自其他线程的干扰访问，并且其中在事务执行期间进行的改变不会被提交直到事务执行完成而不遇到 干扰来自另一个线程的数据访问。 在事务性程序执行期间遇到存储器位置的释放指令时，系统修改处理器内的状态信息以从监视释放存储器位置。 该系统还执行commit-and-start-new-transaction指令，其中commit-and-start-new-transaction指令以原子方式提交事务的存储，从而在事务的读取集保持不受影响的情况下将其从事务的写入集中移除。
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4.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07089374B2
公开(公告)日：2006-08-08
申请号：US10764412
申请日：2004-01-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
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5.发明授权Logical power throttling of instruction decode rate for successive time periods 有权连续时间段的逻辑功率节制指令解码速率公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
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公开(公告)号：US20100268919A1
公开(公告)日：2010-10-21
申请号：US12426550
申请日：2009-04-20
申请人： Shailender Chaudhry , Marc Tremblay
发明人： Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30112 , G06F9/30138 , G06F9/3838 , G06F9/384
摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
摘要翻译： 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。
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7.发明申请CHECKPOINTING IN A PROCESSOR THAT SUPPORTS SIMULTANEOUS SPECULATIVE THREADING 审中-公开在支持同时进行线性加工的处理器中进行检查公开(公告)号：US20100031084A1
公开(公告)日：2010-02-04
申请号：US12185683
申请日：2008-08-04
申请人： Marc Tremblay , Shailender Chaudhry
发明人： Marc Tremblay , Shailender Chaudhry
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G06F9/30043 , G06F9/3005 , G06F9/30127 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Embodiments of the present invention provide a system for executing program code on a processor. In these embodiments, the processor is configured to start by using a primary strand to execute program code. Upon detecting a predetermined condition, the processor is configured to instantaneously checkpoint an architectural state of the primary strand and then use the subordinate strand to copy the checkpointed state to memory while using the primary strand to continue executing the program code without interruption.
摘要翻译： 本发明的实施例提供一种用于在处理器上执行程序代码的系统。 在这些实施例中，处理器被配置为通过使用主链来执行程序代码。 在检测到预定条件时，处理器被配置为立即检查主链的架构状态，然后使用下级链将检查点状态复制到存储器，同时使用主链继续执行程序代码而不中断。
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公开(公告)号：US07610470B2
公开(公告)日：2009-10-27
申请号：US11703462
申请日：2007-02-06
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863
摘要： One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread. While executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the system uses the second thread to execute the deferred instruction to produce a result and forwards the result to be used by subsequent deferred instructions without committing the result to the architectural state of the destination register. Hence, the system makes the result available to the subsequent deferred instructions without overwriting the result produced by a following non-deferred instruction.
摘要翻译： 本发明的一个实施例提供一种在同时推测的线程中防止数据危害的系统。 系统通过使用第一个线程以执行模式执行指令来启动。 在执行执行模式下执行指令时，系统维护每个寄存器的依赖信息，指示寄存器是否受到未解析的数据依赖。 在执行提前模式下解析数据依赖关系时，系统将依赖关系信息复制到依赖关系信息的推测性副本。 然后，系统使用第二个线程以延迟模式开始执行延迟指令。 在延迟模式下执行指令时，如果目的寄存器的依赖关系信息的推测性副本指示在执行提前模式下由第一线程执行的后续非延迟指令存在写后写入（WAW）危险 ，系统使用第二个线程执行延迟指令以产生结果，并转发后续延迟指令使用的结果，而不将结果提交到目标寄存器的体系结构状态。 因此，系统使结果可用于后续延期指令，而不会覆盖由以下非延迟指令产生的结果。
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9.发明授权Generation of multiple checkpoints in a processor that supports speculative execution 有权在支持推测性执行的处理器中生成多个检查点公开(公告)号：US07571304B2
公开(公告)日：2009-08-04
申请号：US11084655
申请日：2005-03-18
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3842
摘要： One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.
摘要翻译： 本发明的一个实施例提供一种在支持推测执行的处理器中创建多个检查点的系统。 系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。 在使处理器进入执行模式的指令期间遇到启动条件时，系统执行初始检查点并以执行提前模式开始执行指令。 在执行提前模式期间遇到预定义的条件时，系统生成附加检查点，并以执行提前模式继续执行指令。 如果处理器随后遇到需要处理器返回到检查点的条件，则生成附加检查点将允许处理器返回到附加检查点，而不是先前检查点。
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10.发明授权Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level 有权在L1高速缓存级别执行存储器引用排序要求的方法和装置公开(公告)号：US07523266B2
公开(公告)日：2009-04-21
申请号：US11592836
申请日：2006-11-03
申请人： Shailender Chaudhry , Marc Tremblay
发明人： Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30189 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.
摘要翻译： 本发明的一个实施例提供了一种在多处理器中的级别1（L1）高速缓存上实施存储器参考排序要求（诸如总存储订购（TSO））的系统。 在操作期间，当以推测执行模式执行指令时，系统在L1高速缓存中接收用于高速缓存线的无效信号，其中从多处理器内的高速缓存相干系统接收到无效信号。 响应于无效信号，如果高速缓存行存在于L1高速缓存中，则系统检查高速缓存行中的加载标记，其中设置的加载标记指示在推测执行期间已经加载了高速缓存行。 如果设置了加载标记，则系统将失败推测执行模式，并从检查点恢复正常执行模式。 通过失败推测执行模式，系统确保由无效信号指示的高速缓存行的潜在更新不会导致在推测执行模式期间违反存储器引用排序要求。
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