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    Field effect transistors with channels oriented to different crystal planes
    3.
    发明授权
    Field effect transistors with channels oriented to different crystal planes 有权
    场效应晶体管，通道定向到不同的晶面

    公开(公告)号：US07915713B2

    公开(公告)日：2011-03-29

    申请号：US12182419

    申请日：2008-07-30

    申请人： Juergen Faul ,  Juergen Holz

    发明人： Juergen Faul ,  Juergen Holz

    IPC分类号： H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4236 ,  H01L29/7827

    摘要： An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

    摘要翻译： 集成电路包括第一载流子类型的第一场效应晶体管和第二不同载流子类型的第二场效应晶体管。 在导通状态下，第一场效应晶体管的第一通道被定向到半导体衬底的第一组等效晶面中的一个，第二场效应晶体管的第二沟道被定向到第二场效应晶体管中的至少一个， 不同组的等效晶面。 第一组等效晶面平行于半导体衬底的主表面，第二组等效晶面垂直于主表面。

    Geometrical control of device corner threshold
    4.
    发明授权
    Geometrical control of device corner threshold 失效

    公开(公告)号：US5858866A

    公开(公告)日：1999-01-12

    申请号：US753234

    申请日：1996-11-22

    申请人： Wayne S. Berry ,  Juergen Faul ,  Wilfried Haensch ,  Rick L. Mohler

    发明人： Wayne S. Berry ,  Juergen Faul ,  Wilfried Haensch ,  Rick L. Mohler

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/336

    CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L21/823456 ,  Y10S977/888 ,  Y10S977/938

    摘要： Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.

    INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE
    5.
    发明申请
    INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE 审中-公开
    具有分离功能门的集成电路

    公开(公告)号：US20080308870A1

    公开(公告)日：2008-12-18

    申请号：US11763796

    申请日：2007-06-15

    申请人： Juergen Faul ,  Stefan Slesazeck ,  Martin Popp ,  Rolf Weis

    发明人： Juergen Faul ,  Stefan Slesazeck ,  Martin Popp ,  Rolf Weis

    IPC分类号： H01L29/76

    CPC分类号： H01L29/4983 ,  H01L27/10823 ,  H01L27/10838 ,  H01L27/10873 ,  H01L29/78

    摘要： An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV.

    摘要翻译： 公开了一种集成电路。 一个实施例提供了一种场效应晶体管，其包括栅电极，沟道区和第一源极/漏极区。 栅电极可以包括确定栅极电极和沟道区域之间的第一平坦带电压的主部分和与主部分接触的第一横向部分，并且确定栅电极和第一电极之间的第二平带电压 源/漏区。 第一和第二平带电压相差至少0.1eV。

    Geometrical control of device corner threshold
    7.
    发明授权
    Geometrical control of device corner threshold 失效

    公开(公告)号：US5998852A

    公开(公告)日：1999-12-07

    申请号：US78517

    申请日：1998-05-15

    申请人： Wayne S. Berry ,  Juergen Faul ,  Wilfried Haensch ,  Rick L. Mohler

    发明人： Wayne S. Berry ,  Juergen Faul ,  Wilfried Haensch ,  Rick L. Mohler

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/00

    CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L21/823456 ,  Y10S977/888 ,  Y10S977/938

    摘要： Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.

    Methods of forming bulk FinFET devices so as to reduce punch through leakage currents
    8.
    发明授权
    Methods of forming bulk FinFET devices so as to reduce punch through leakage currents 有权
    形成散装FinFET器件的方法，以减少穿透漏电流

    公开(公告)号：US09023715B2

    公开(公告)日：2015-05-05

    申请号：US13454520

    申请日：2012-04-24

    申请人： Juergen Faul ,  Frank Jakubowski

    发明人： Juergen Faul ,  Frank Jakubowski

    IPC分类号： H01L21/225 ,  H01L29/66

    CPC分类号： H01L21/2255 ,  H01L29/66803

    摘要： Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.

    摘要翻译： 公开了形成体FinFET半导体器件以减少穿透漏电流的方法。 一个实例包括在半导体衬底中形成多个沟槽以限定多个间隔开的散热片，在沟槽中形成绝缘材料的掺杂层，其中每个鳍的暴露部分在掺杂的上表面上方延伸 绝缘材料层，而每个鳍片的覆盖部分位于绝缘材料的掺杂层的上表面的下方，并且进行加工操作以至少加热绝缘材料的掺杂层，以使掺杂物质掺杂 层从绝缘材料的掺杂层迁移到鳍的被覆盖部分中，从而在翅片的被覆盖部分中限定位于翅片的暴露部分下方的掺杂区域。

    Transistor, memory cell, memory cell array and method of forming a memory cell array
    9.
    发明授权
    Transistor, memory cell, memory cell array and method of forming a memory cell array 失效
    晶体管，存储单元，存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US07700983B2

    公开(公告)日：2010-04-20

    申请号：US11300853

    申请日：2005-12-15

    申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

    摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

    摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

    Field Effect Transistors with Channels Oriented to Different Crystal Planes
    10.
    发明申请
    Field Effect Transistors with Channels Oriented to Different Crystal Planes 有权
    具有通向不同水晶平面的通道的场效应晶体管

    公开(公告)号：US20100025826A1

    公开(公告)日：2010-02-04

    申请号：US12182419

    申请日：2008-07-30

    申请人： Juergen Faul ,  Juergen Holz

    发明人： Juergen Faul ,  Juergen Holz

    IPC分类号： H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823885 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4236 ,  H01L29/7827

    摘要： An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

    摘要翻译： 集成电路包括第一载流子类型的第一场效应晶体管和第二不同载流子类型的第二场效应晶体管。 在导通状态下，第一场效应晶体管的第一通道被定向到半导体衬底的第一组等效晶面中的一个，第二场效应晶体管的第二沟道被定向到第二场效应晶体管中的至少一个， 不同组的等效晶面。 第一组等效晶面平行于半导体衬底的主表面，第二组等效晶面垂直于主表面。