公开(公告)号：US08754459B2

公开(公告)日：2014-06-17

申请号：US13728311

申请日：2012-12-27

申请人： Masaaki Higuchi ,  Masaru Kito

发明人： Masaaki Higuchi ,  Masaru Kito

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/11 ,  H01L27/115 ,  H01L21/8229 ,  H01L21/8239 ,  H01L27/112 ,  H01L29/68

CPC分类号： H01L27/105 ,  H01L21/8229 ,  H01L21/8239 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/685 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，多个绝缘分离膜，通道体和存储膜。 层叠体包括多个电极层和多个绝缘层。 多个绝缘分离膜将堆叠体分离成多个。 通道体在层叠方向上在多个绝缘分离膜之间延伸。 绝缘分离膜和记忆膜之间的下层侧的电极层的宽度大于绝缘分离膜和记忆膜之间的上层侧的电极层的宽度。 对于具有比具有较小宽度的上层侧的电极层的宽度大的下层侧的电极层，电极层的电阻率较高。

公开(公告)号：US20140061773A1

公开(公告)日：2014-03-06

申请号：US13728311

申请日：2012-12-27

申请人： Masaaki HIGUCHI ,  Masaru Kito

发明人： Masaaki HIGUCHI ,  Masaru Kito

IPC分类号： H01L29/792

CPC分类号： H01L27/105 ,  H01L21/8229 ,  H01L21/8239 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/685 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，多个绝缘分离膜，通道体和存储膜。 层叠体包括多个电极层和多个绝缘层。 多个绝缘分离膜将堆叠体分离成多个。 通道体在层叠方向上在多个绝缘分离膜之间延伸。 绝缘分离膜和记忆膜之间的下层侧的电极层的宽度大于绝缘分离膜和记忆膜之间的上层侧的电极层的宽度。 对于具有比具有较小宽度的上层侧的电极层的宽度大的下层侧的电极层，电极层的电阻率较高。

公开(公告)号：US08916921B2

公开(公告)日：2014-12-23

申请号：US12705088

申请日：2010-02-12

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

IPC分类号： H01L29/792 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2

摘要翻译： 多个第一导电层在垂直方向上以一定间隔L设置，夹在其间的电介质。 设定一定间隔L使得第一电介质具有满足以下关系式（1）的等效氧化物厚度DEOT。 Dsio2

公开(公告)号：US08847303B2

公开(公告)日：2014-09-30

申请号：US13422294

申请日：2012-03-16

申请人： Masaru Kito ,  Ryota Katsumata

发明人： Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.

摘要翻译： 根据一个实施例，半导体器件包括：衬底; 设置在所述基板上方的堆叠体，包括设置在所述选择器门上的选择栅和绝缘层; 设置在沿层叠方向穿过层叠体而形成的孔的侧壁上的绝缘膜; 通道体和半导体层。 通道体设置在孔中的绝缘膜的侧壁上，其阻挡在选择栅中的绝缘层侧的端部附近的孔，并且在封闭孔的部分下方包围空腔。 半导体层由与沟道体相同的材料形成，并且被连续地嵌入在通道体阻挡孔的部分上方的孔中。

公开(公告)号：US08760924B2

公开(公告)日：2014-06-24

申请号：US13427263

申请日：2012-03-22

申请人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

发明人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

公开(公告)号：US08659070B2

公开(公告)日：2014-02-25

申请号：US12561451

申请日：2009-09-17

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。

公开(公告)号：US08426976B2

公开(公告)日：2013-04-23

申请号：US12392636

申请日：2009-02-25

申请人： Megumi Ishiduki ,  Hideaki Aochi ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Yasuyuki Matsuoka

发明人： Megumi Ishiduki ,  Hideaki Aochi ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的柱状半导体层; 多个导电层，经由存储层形成在所述柱状半导体层的侧壁处; 以及形成在导电层下方的层间绝缘层。 形成面向柱状半导体层的导电层的侧壁，使得其与柱状半导体层的中心轴的距离在其下部位置比在其上部位置变大。 同时，面对柱状半导体层的层间绝缘层的侧壁形成为倾斜，使得其在柱状半导体层的中心轴线处的距离在其下部位置处比在其上部位置变小。

公开(公告)号：US08426276B2

公开(公告)日：2013-04-23

申请号：US13365600

申请日：2012-02-03

申请人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/8234

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的第一柱状半导体层; 电荷累积层，经由第一气隙形成在第一柱状半导体层上，并积累电荷; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个第一导电层。

公开(公告)号：US20130021848A1

公开(公告)日：2013-01-24

申请号：US13427263

申请日：2012-03-22

申请人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

发明人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

公开(公告)号：US08350314B2

公开(公告)日：2013-01-08

申请号：US12325711

申请日：2008-12-01

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括多个存储器串，每个存储器串由多个电可擦除存储器单元组成，所述多个电可擦除存储器单元串联连接，所述存储器串包括 ：向衬底垂直延伸的柱状半导体层; 多个导电层平行于衬底形成并且包括柱状半导体层的侧壁之间的第一空间; 并且特征变化层形成在面向面向第一空间的导电层的第一空间或侧壁的柱状半导体层的侧壁上，并且伴随施加电压的变化特性; 其中所述多个所述导电层具有对于所述柱状半导体层相对于规定方向的相对移动的功能。