公开(公告)号：US07968733B2

公开(公告)日：2011-06-28

申请号：US12308067

申请日：2007-05-23

申请人： Masaaki Suzuki ,  Kyouji Furuta ,  Toshiaki Minami ,  Seiji Ito

发明人： Masaaki Suzuki ,  Kyouji Furuta ,  Toshiaki Minami ,  Seiji Ito

IPC分类号： C07D207/00

CPC分类号： C07D207/16

摘要： To provide a pyrrolidine analogue having an inhibitory activity on the induction of allodynia, a method for producing the pyrrolidine analogue, and an agent for preventing a neurogenic pain.A pyrrolidine analogue which is a compound represented by the general formula (I) [wherein HOOC-φ represents an aromatic substituent having at least one carboxy group attached to the benzene ring] or a salt or ester of the compound. The compound has a potent inhibitory effect on the induction of allodynia.

摘要翻译： 提供对诱导异常性疼痛具有抑制活性的吡咯烷类似物，制备吡咯烷类似物的方法和用于预防神经性疼痛的药剂。 作为由通式（I）表示的化合物的吡咯烷类似物[其中HOOC-＆phgr; 表示具有至少一个与苯环连接的羧基的芳族取代基]或该化合物的盐或酯。 该化合物对异常性疼痛的诱导具有有效的抑制作用。

公开(公告)号：US20090306407A1

公开(公告)日：2009-12-10

申请号：US12308067

申请日：2007-05-23

申请人： Masaaki Suzuki ,  Kyouji Furuta ,  Toshiaki Minami ,  Seiji Ito

发明人： Masaaki Suzuki ,  Kyouji Furuta ,  Toshiaki Minami ,  Seiji Ito

IPC分类号： C07D207/16 ,  A61P29/00

CPC分类号： C07D207/16

摘要： [Problems]To provide a pyrrolidine analogue having an inhibitory activity on the induction of allodynia, a method for producing the pyrrolidine analogue, and an agent for preventing a neurogenic pain.[Means for Solving the Problems]A pyrrolidine analogue which is a compound represented by the general formula (I) [wherein HOOC-φ represents an aromatic substituent having at least one carboxy group attached to the benzene ring] or a salt or ester of the compound. The compound has a potent inhibitory effect on the induction of allodynia.

摘要翻译： [问题]提供对诱导异常性疼痛具有抑制活性的吡咯烷类似物，制备吡咯烷类似物的方法和用于预防神经性疼痛的药剂。 [解决问题的手段]作为通式（I）表示的化合物的吡咯烷类似物[其中HOOC-phi表示具有至少一个与苯环连接的羧基的芳香族取代基]或其中的 复合。 该化合物对异常性疼痛的诱导具有有效的抑制作用。

公开(公告)号：US08108562B2

公开(公告)日：2012-01-31

申请号：US12585140

申请日：2009-09-04

申请人： Kousuke Komikado ,  Koji Iwamitsu ,  Tetsuya Shirogane ,  Atsushi Ishikawa ,  Takahide Okuno ,  Mitsuhide Sato ,  Toshiaki Minami ,  Hiroaki Yuasa

发明人： Kousuke Komikado ,  Koji Iwamitsu ,  Tetsuya Shirogane ,  Atsushi Ishikawa ,  Takahide Okuno ,  Mitsuhide Sato ,  Toshiaki Minami ,  Hiroaki Yuasa

IPC分类号： G06F3/00 ,  G06F15/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0689 ,  G06F2206/1012

摘要： Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores. Each of the plurality of cores processes the command to the logical unit to be handled by a self core based on the association information and executes I/O processing of the data to the logical unit.

摘要翻译： 提供了一种能够通过平衡处理器和控制器上的负载来提高数据处理速度的存储子系统。 该存储子系统包括用于控制向存储装置输入和输出数据的控制器，向存储装置提供多个逻辑单元以成为主计算机读取和写入数据的存储范围，处理发出的命令 并且具有与逻辑单元相关的存储资源。 控制器具有用于存储该命令的本地存储器，以及由多个核心构成的处理器，用于根据该命令来控制向逻辑单元输入和输出数据以进行数据的输入和输出。 本地存储器存储表示多个逻辑单元与多个核心之间的对应关系的关联信息。 多个核心中的每一个都基于该关联信息将该命令处理为由自核心处理的逻辑单元，并且将该数据的I / O处理执行到该逻辑单元。

公开(公告)号：US20100223409A1

公开(公告)日：2010-09-02

申请号：US12095599

申请日：2007-06-12

申请人： Toshiaki Minami ,  Shunichi Kaizu ,  Yasunari Nagamatsu ,  Daisuke Shiraishi ,  Makoto Fujiwara ,  Koji Moriya ,  Koichi Morishita

发明人： Toshiaki Minami ,  Shunichi Kaizu ,  Yasunari Nagamatsu ,  Daisuke Shiraishi ,  Makoto Fujiwara ,  Koji Moriya ,  Koichi Morishita

IPC分类号： G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362

摘要： A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

摘要翻译： 根据本发明的总线仲裁装置适当地仲裁多个主机和多个从机之间的总线使用权，以便有效地执行所请求的数据传送。 仲裁器A 5接收由主设备A 1和B 2生成的从设备A 3的数据传送请求。仲裁器A 5与仲裁器B 4协同工作，并且仲裁关于从设备A的数据传送请求的争用 3由主人A 1和B 2生成。

公开(公告)号：US07734410B2

公开(公告)日：2010-06-08

申请号：US11711044

申请日：2007-02-27

申请人： Yasuhiro Tooyama ,  Toshiaki Minami ,  Naoko Aoyanagi

发明人： Yasuhiro Tooyama ,  Toshiaki Minami ,  Naoko Aoyanagi

IPC分类号： G01C21/00

CPC分类号： G01C21/3694 ,  G08G1/0969

摘要： When a display map information is reduced to a specified scale for a wide area, items of congestion information are extracted which have a congestion level of “congested or busy”, and an overlap determination area is created for a congestion link of each item of extracted congestion information. The overlap determination area extends both transversely and longitudinally for a specified distance from the congestion link. Also, for each group of congestion information items having overlapping determination areas, an equal congestion level area is created by connecting the overlap determination areas and displayed in a color that corresponds to the congestion level. Equal congestion level areas are also created in the same manner for the congestion information items with congestion levels of “congested” and “not congested”, and displayed in different colors that correspond to their respective congestion levels.

摘要翻译： 当显示地图信息被减小到广域的规定尺度时，提取具有“拥挤或忙碌”拥塞级别的拥塞信息的项目，并且为提取的每个项目的拥塞链路创建重叠确定区域 拥塞信息。 重叠确定区域横向和纵向延伸距离拥塞链路一定距离。 此外，对于具有重叠的确定区域的每个拥塞信息项目组，通过连接重叠确定区域并以与拥塞水平相对应的颜色来显示相等拥塞水平区域。 对于具有“拥塞”和“不拥塞”的拥塞级别的拥塞信息项也以相同的方式创建相等的拥塞级别区域，并且以与它们各自的拥塞级别对应的不同颜色显示。

公开(公告)号：US07716387B2

公开(公告)日：2010-05-11

申请号：US11485285

申请日：2006-07-13

申请人： Toshiaki Minami

发明人： Toshiaki Minami

IPC分类号： G06F12/00

CPC分类号： G06F13/1626

摘要： A memory control apparatus generates a plurality of commands whose unit of transfer is smaller than the unit of data transfer of a memory access request, and when the memory access request are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request are executed by time division and concurrently.

摘要翻译： 存储器控制装置生成传送单位小于存储器访问请求的数据传送单位的多个命令，并且当从多个请求源发送存储器访问请求时，将多个命令发布到存储器 每个请求的交替顺序是通过时分和并发执行的。

公开(公告)号：US07199472B2

公开(公告)日：2007-04-03

申请号：US10970027

申请日：2004-10-22

申请人： Toshiaki Minami ,  Toshiyuki Sakuta ,  Makoto Kuwata

发明人： Toshiaki Minami ,  Toshiyuki Sakuta ,  Makoto Kuwata

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10162 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

摘要翻译： 在由铝构成的最上层布线层和由铜构成的正下方的布线层的半导体装置中，最上层的布线层比其正下方的布线层厚，因此最上层布线层的薄层电阻比 接线层正下方。 多环电源线VR和焊盘PD由最上层布线层形成，环形电源线VR和焊盘PD分别通过最上层布线层的电力线VLB1连接。 因此，可以减小从焊盘PD到环形电源线VR的馈电路径上的电压降，并且可以稳定从焊盘PD到环形电源线VR的电力传导。

公开(公告)号：US20070043910A1

公开(公告)日：2007-02-22

申请号：US11585210

申请日：2006-10-24

申请人： Toshiaki Minami

发明人： Toshiaki Minami

IPC分类号： G06F12/00

CPC分类号： G06F13/1673

摘要： A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

摘要翻译： 存储器控制器根据来自多个主器件的请求从DRAM读取数据。 它包括用于存储预读操作的结果的预取缓冲器和用于在多个主器件中设置特定主器件的寄存器。 当主机请求读取时，存储器控制器预先读取所请求数据之后的数据，并且确定主机是否是由寄存器设置的特定主机。 如果主机是由寄存器设置的特定主机，则预读取的结果存储在预取缓冲器中。 因此，预取缓冲器可以在具有多个主器件的系统中有效地起作用。

公开(公告)号：US20070016699A1

公开(公告)日：2007-01-18

申请号：US11485285

申请日：2006-07-13

申请人： Toshiaki Minami

发明人： Toshiaki Minami

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/1626

摘要： A flower arrangement that appears to be a cake. A piece of foam, shaped in the shape of a cake, having flowers inserted into the foam, and then placed on a cake plate or platter, and then placed in a cake box.

摘要翻译： 一个似乎是蛋糕的花卉安排。 一块形状为蛋糕形状的泡沫，将花插入泡沫中，然后放在蛋糕盘或盘子上，然后放在蛋糕盒中。

公开(公告)号：US20060004511A1

公开(公告)日：2006-01-05

申请号：US11171462

申请日：2005-07-01

申请人： Kazutaka Yoshikawa ,  Hiroshi Tomita ,  Toshiaki Minami ,  Kenji Nagase

发明人： Kazutaka Yoshikawa ,  Hiroshi Tomita ,  Toshiaki Minami ,  Kenji Nagase

IPC分类号： G01C21/30

CPC分类号： G08G1/096827 ,  G01C21/3492

摘要： A navigation system, traffic prediction method, and traffic prediction program search for a plurality of routes to a destination. The system, method, and program calculate, if any of the plurality of routes passes through a predetermined area, a predicted time at which a link within the predetermined area will be passed through. The system, method, and program generate predicted traffic information for the link at the predicted time at which the link will be passed through based on the stored traffic information.

摘要翻译： 导航系统，交通预测方法和交通预测程序搜索到目的地的多条路线。 如果多条路线中的任一条通过预定区域，则系统，方法和程序计算预定区域内的链路将通过的预测时间。 系统，方法和程序根据所存储的交通信息，在链接将被传递的预测时间产生链路的预测交通信息。