公开(公告)号：US4498175A

公开(公告)日：1985-02-05

申请号：US430002

申请日：1982-09-30

申请人： Masahide Nagumo ,  Jun Inagawa ,  Tadashi Kojima

发明人： Masahide Nagumo ,  Jun Inagawa ,  Tadashi Kojima

IPC分类号： G06F11/10 ,  G06F7/72 ,  G11B7/00 ,  G11B7/004 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15

CPC分类号： H03M13/151 ,  G06F7/724 ,  G06F7/726 ,  G11B20/1809

摘要： An error correcting system uses an error location polynomial which is defined by double correction BCH codes each consisting of the elements of a Galois field GF(2.sup.m), and thereby generates error locations .sigma..sub.1 and .alpha..sup.2 and error patterns e.sub.1 and 2.sub.2. The system has a first data processing system for performing only addition and multiplication to generate the error locations .sigma..sub.1 and .alpha..sup.2, and a second data processing system for performing only addition and multiplication to generate the error patterns e.sub.1 and 2.sub.2. The first data processing system comprises a syndrome generator, a memory, an arithmetic logic unit, registers, latch circuits, registers, adder circuits and a zero detector. The second data processing system comprises a gate circuit, latch circuits, an arithmetic logic unit, and the registers of a memory.

摘要翻译： 误差校正系统使用错误位置多项式，该多项式由由Galois域GF（2m）的元素组成的双校正BCH码定义，从而产生误差位置sigma1和α2以及误差模式e1和22。 具有用于仅执行加法和乘法以产生错误位置sigma1和alpha2的第一数据处理系统，以及仅执行相加和相乘以产生错误模式e1和22的第二数据处理系统。第一数据处理系统包括 校正子发生器，存储器，算术逻辑单元，寄存器，锁存电路，寄存器，加法器电路和零检测器。 第二数据处理系统包括门电路，锁存电路，算术逻辑单元和存储器的寄存器。

公开(公告)号：US4608692A

公开(公告)日：1986-08-26

申请号：US647919

申请日：1984-09-06

申请人： Masahide Nagumo ,  Tadashi Kojima ,  Jun Inagawa

发明人： Masahide Nagumo ,  Tadashi Kojima ,  Jun Inagawa

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H03M13/151

摘要： An error correction circuit in which an error location polynomial is determined on the basis of the code word of the code of a double correction BCH symbol in Galois field GF(2.sup.m), thereby determining the error location and error pattern necessary for the error correction. The error correction circuit includes: (a) means for generating a syndrome S.sub.i (i being an integer) from the code word: (b) first and second means for holding S.sub.1 and S.sub.0 out of the syndromes outputted from the syndrome generating means; (c) means for effecting the following calculation on the basis of the syndrome generated by the syndrome generating means:r.sub.3 =S.sub.2 S.sub.0 +S.sub.1.sup.2r.sub.2 =S.sub.3 S.sub.0 +S.sub.1 S.sub.2r.sub.1 =S.sub.3 S.sub.1 +S.sub.2.sup.2third means for holding r.sub.3 out of r.sub.3, r.sub.2 and r.sub.1 ; (d) means for judging whether r.sub.3 out of r.sub.3, r.sub.2 and r.sub.1 satisfy the condition: r.sub.3 .noteq.0 or r.sub.3 =0; (e) a control means for making, when the condition: r.sub.3 .noteq.0 is confirmed by the judging means, the first and second holding means holding r.sub.1 and r.sub.2 in place of S.sub.1 ad S.sub.0 ; and (f) means for processing signals, which is adapted to add a value obtained through multiplying the content S.sub.1 or r.sub.1 of the first holding means and the content S.sub.0 or r.sub.2 of the second holding means by the element .alpha..sup.i of the Galois field GF(2.sup.m) to a value of the third holding means with .alpha..sup.2i, whereby the element .alpha..sup.i as obtained when the output from the signal processing means is reduced to zero is used as the error location.

摘要翻译： 一种误差校正电路，其中基于伽罗瓦域GF（2m）中的双校正BCH码元的码的码字来确定误差位置多项式，从而确定纠错所需的误差位置和误差模式。 误差校正电路包括：（a）从码字产生校正子Si（i为整数）的装置：（b）用于从校正子发生装置输出的校正子中保持S1和S0的第一和第二装置; （c）基于由校正子产生装置产生的校正子进行以下计算的装置：r3 = S2S0 + S12r2 = S3S0 + S1S2 r1 = S3S1 + S22用于将r3保持在r3，r2和r1之外的第三装置; （d）用于判断r3，r2和r1中的r3是否满足条件：r3 NOTEQUAL 0或r3 = 0; （e）控制装置，当判断装置确认条件：r3 NOTEQUAL 0时，保持r1和r2的第一和第二保持装置代替S1广告S0; （f）用于处理信号的装置，其适于将通过将第一保持装置的内容S1或r1与第二保持装置的内容S0或r2相乘得到的值加上伽罗瓦域GF的元素αi （2m）到具有α2i的第三保持装置的值，由此将来自信号处理装置的输出减少为零时获得的元素αi用作错误位置。

公开(公告)号：US4567568A

公开(公告)日：1986-01-28

申请号：US473767

申请日：1983-03-10

申请人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

发明人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

IPC分类号： G06F11/10 ,  G06F1/03 ,  G06F7/72 ,  G11B20/18 ,  H03M13/15 ,  G06F7/52

CPC分类号： G06F7/726 ,  G11B20/1809 ,  H03M13/15 ,  G06F1/0307

摘要： Data representing one element .alpha..sup.i of a Galois field GF(2.sup.m) are stored in a first linear shift register, and data representing another element .alpha..sup.j of the Galois field GF(2.sup.m) are stored in a second linear shift register. 2.sup.m elements of Galois field GF(2.sup.m) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter which includes a decoder and an encoder. The data representing element .alpha..sup.j are supplied from the second linear shift register to the decoder. If the data representing the reciprocal of element .alpha..sup.j are stored in the converter, they are read from the encoder. If they are not stored in the converter, the first linear shift register and the second linear shift register are shifted N times by control pulses generated by a NOR gate and an AND gate until any one of the reciprocal data are read from the encoder, whereby the register supplies data representing .alpha..sup.i+N and the register supplies data representing .alpha..sup.- (j+N). A multiplier multiplies element .alpha..sup.i by reciprocal .alpha..sup.j or multiplies element .alpha..sup.i+N by reciprocal .alpha..sup.-(j+N), thereby performing the division: a.sup.i .div..alpha..sup.j (=.alpha..sup.i-j).

摘要翻译： 表示伽罗瓦域GF（2m）的一个元素αi的数据被存储在第一线性移位寄存器中，并且表示伽罗瓦域GF（2m）的另一元素αj的数据被存储在第二线性移位寄存器中。 伽罗瓦域GF（2m）的2m元素分为n组。 分别位于n组的特定位置的n个元件的倒数表存储在包括解码器和编码器的转换器中。 表示元素αj的数据从第二线性移位寄存器提供给解码器。 如果表示元素αj的倒数的数据存储在转换器中，则从编码器读取它们。 如果它们不存储在转换器中，则通过由或非门和与门产生的控制脉冲将第一线性移位寄存器和第二线性移位寄存器移位N次，直到从编码器读取任何一个倒数数据，由此 寄存器提供表示αi + N的数据，寄存器提供表示α - （j + N）的数据。 乘法器将元素αi乘以相等的αj或乘以元素αi + N通过倒数α - （j + N），从而执行除法：ai DIVIDEDαj（=αi-j）。

公开(公告)号：US4574361A

公开(公告)日：1986-03-04

申请号：US473765

申请日：1983-03-10

申请人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

发明人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

IPC分类号： G06F7/52 ,  G06F7/72 ,  G06F11/10 ,  G11B20/18 ,  H03M13/15

CPC分类号： H03M13/15 ,  G06F7/726 ,  G11B20/1809

摘要： An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. "1" detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any "1" detector circuit detects "1" in response to output signals from a 2-input AND gate. When "1" is detected, a NOR gate supplies a signal of logical "0" to the AND gate, whereby the AND gate stops supplying output signals. 2-input AND circuits are connected at one input terminal to the outputs of the "1" detector circuits and at the other input terminal to the outputs of the second linear shift registers. The AND circuit connected to the "1" detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division .alpha..sup.i -.alpha..sup.j, are delivered through an OR circuit.

摘要翻译： 一种装置将伽罗瓦域GF（2m）的一个元素αi除以场的另一元素αj。 分频器数据αj通过α1，α2，N2提供给第一线性移位寄存器中的一个并且被提供给其它第一线性移位寄存器。 。 。 乘法器电路。 同时，通过alpha N1，αN2，将分红数据αi提供给第二线性移位寄存器中的一个和另一个第二线性移位寄存器。 。 。 乘法器电路。 “1”检测器电路分别连接到第一线性移位寄存器的输出端。 第一线性移位寄存器和第二线性移位寄存器被移位几次，直到任何“1”检测器电路响应于来自2输入与门的输出信号检测到“1”为止。 当检测到“1”时，或非门向AND门提供逻辑“0”的信号，由此与门停止提供输出信号。 2输入AND电路在一个输入端子连接到“1”检测器电路的输出端，另一个输入端连接到第二线性移位寄存器的输出端。 连接到“1”检测器电路的AND电路提供存储在其所连接的第二线性移位寄存器中的数据。 表示分区αi-αj的商的数据通过OR电路传送。

公开(公告)号：US4453260A

公开(公告)日：1984-06-05

申请号：US423725

申请日：1982-09-27

申请人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

发明人： Jun Inagawa ,  Masahide Nagumo ,  Tadashi Kojima

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B27/30 ,  H04J3/06

CPC分类号： G11B20/1403 ,  G11B20/10527 ,  G11B27/3027

摘要： A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.

摘要翻译： 同步电路包括一个同步信号检测电路，连接用于接收具有多个帧的数字信号，每个帧由N位组成并包含帧同步信号以检测每帧中的同步信号;以及同步保护电路，用于产生同步控制 信号与同步信号的检测同步，并且当没有检测到同步信号时每帧内插同步控制信号。 同步保护电路具有用于计数未检测到同步信号的帧数的计数器。 提供一种电路，用于当由同步信号检测电路产生噪声时，通过同步信号检测电路快速同步同步保护电路与同步信号的检测，然后在给定值已被 计数器。

公开(公告)号：US5553041A

公开(公告)日：1996-09-03

申请号：US419272

申请日：1995-04-10

申请人： Jun Inagawa ,  Masahide Nagumo ,  Kunihiko Kodama

发明人： Jun Inagawa ,  Masahide Nagumo ,  Kunihiko Kodama

IPC分类号： G11B7/00 ,  G06F5/06 ,  G11B7/005 ,  G11B7/09 ,  G11B19/02 ,  G11B19/28 ,  G11B20/10 ,  G11B20/14 ,  H01L27/10

CPC分类号： G11B20/10527 ,  G06F5/06 ,  G11B19/02 ,  G11B20/10 ,  G06F2205/061 ,  G11B2020/10814 ,  G11B2020/10824 ,  G11B7/0946

摘要： An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from going overflow/underflow. Writing information data read from the disc to the buffer memory is performed in synchronism with a reproduction stage clock signal, and reading from the buffer memory is in synchronism with a signal processing stage clock. The signal processing stage clock for reading information data from the buffer memory is changed in accordance with the amount of information data stored in the buffer memory for preventing interruptions in data reproduction.

摘要翻译： 一种用于再现存储在盘上的数据以防止缓冲存储器上溢/下溢的装置，信号处理电路和方法。 将从盘读取的信息数据写入缓冲存储器是与再现级时钟信号同步执行的，并且从缓冲存储器读取与信号处理级时钟同步。 用于从缓冲存储器读取信息数据的信号处理级时钟根据存储在缓冲存储器中的用于防止数据再现中断的信息数据量而改变。

公开(公告)号：US4502024A

公开(公告)日：1985-02-26

申请号：US473763

申请日：1983-03-10

申请人： Meisei Nishikawa ,  Masahide Nagumo ,  Tadashi Kojima

发明人： Meisei Nishikawa ,  Masahide Nagumo ,  Tadashi Kojima

IPC分类号： G11B7/00 ,  G11B19/24 ,  H03K7/08

CPC分类号： G11B19/24 ,  H03K7/08

摘要： The invention provides a pulse-width modulation circuit in which an output from a latch circuit for holding a count obtained by counting a reference clock signal in accordance with the period of a signal to be modulated is compared by a comparator with an output from a ramp counter for counting the reference clock signal at a predetermined period so as to perform a pulse-width modulation. The number of bits of the comparator and the ramp counter is decreased by n bits with respect to the number N (N>n) of bits of the latch circuit.

摘要翻译： 本发明提供了一种脉冲宽度调制电路，其中来自锁存电路的输出用于保持根据待调制信号的周期对参考时钟信号进行计数而获得的计数，通过比较器与斜坡的输出进行比较 计数器，用于以预定周期对参考时钟信号进行计数，以执行脉宽调制。 比较器和斜坡计数器的位数相对于锁存电路的位数N（N> n）减少n位。

公开(公告)号：US4489287A

公开(公告)日：1984-12-18

申请号：US331076

申请日：1981-12-15

申请人： Masahide Nagumo ,  Tadashi Kojima

发明人： Masahide Nagumo ,  Tadashi Kojima

IPC分类号： G11B20/14 ,  H03L7/08 ,  H03L7/087 ,  H03L7/197 ,  H04L7/033 ,  H03L7/22 ,  H04N5/95

CPC分类号： H03L7/1974 ,  H03L7/08 ,  H03L7/087

摘要： A phase sychronizing circuit for a device which reproduces digital data has a phase locked loop including a first phase comparison circuit, a voltage controlled oscillator (VCO) producing an output the frequency of which is controlled by the first phase comparison circuit, and a first frequency divider to divide the output frequency of the VCO. The phase synchronizing circuit further includes second frequency divider for dividing the output frequency of the VCO, a second phase comparison circuit for comparing the phase of a first clock signal from the first frequency divider, with that of a second clock signal from the second frequency divider and a circuit for controlling the frequency dividing ratio of the first frequency dividing circuit according to the phase difference between the first and second clock signals in such a way that the frequency dividing ratio becomes one of 1/N, 1/(N+1) and 1/{(N+(N+1))/2} wherein N is a positive integer.

摘要翻译： 用于再现数字数据的装置的相位同步电路具有锁相环，该锁相环包括第一相位比较电路，产生其频率由第一相位比较电路控制的输出的压控振荡器（VCO）和第一频率 分频器来分频VCO的输出频率。 相位同步电路还包括用于分频VCO的输出频率的第二分频器，用于比较来自第一分频器的第一时钟信号的相位与来自第二分频器的第二时钟信号的相位的第二相位比较电路 以及用于根据第一和第二时钟信号之间的相位差来控制第一分频电路的分频比的电路，使得分频比变为1 / N，1 /（N + 1）之一， 和1 / {（N +（N + 1））/ 2}其中N是正整数。

公开(公告)号：US4710923A

公开(公告)日：1987-12-01

申请号：US792890

申请日：1985-10-30

申请人： Masahide Nagumo

发明人： Masahide Nagumo

IPC分类号： G11B20/12 ,  G11B20/18 ,  G06F11/10

CPC分类号： G11B20/1809

摘要： A control system for deinterleaving memories in a digital audio reproducing apparatus. A plurality of cross-interleaved symbols are written into or read out from the memory areas of a RAM. The control system includes three processors for controlling the symbols. The first processor prepares a memory area with a predetermined storage capacity in the RAM. The second processor reads and writes the first symbol of a plurality of cross-interleave symbols into the memory area. The third processor likewise reads and writes the second symbol into the memory area. The second processor includes a counter for determining the address. The third processor includes an adder producing a sum of the counter output and a fixed amount to determine the second address.

摘要翻译： 一种用于在数字音频再现装置中对存储器进行解交织的控制系统。 多个交叉交织的符号被写入RAM或从RAM的存储区读出。 控制系统包括用于控制符号的三个处理器。 第一处理器在RAM中准备具有预定存储容量的存储区。 第二处理器将多个交叉交织符号的第一符号读取并写入到存储器区域中。 第三处理器同样读取并将第二符号写入存储器区域。 第二处理器包括用于确定地址的计数器。 第三处理器包括产生计数器输出和固定量之和以确定第二地址的加法器。

公开(公告)号：US4366448A

公开(公告)日：1982-12-28

申请号：US134303

申请日：1980-03-26

申请人： Hiromi Kusakabe ,  Masahide Nagumo

发明人： Hiromi Kusakabe ,  Masahide Nagumo

IPC分类号： H03F1/34 ,  H03F3/30 ,  H03F3/26

CPC分类号： H03F3/3066 ,  H03F1/34 ,  H03F3/3093

摘要： A power-amplifying circuit embodying this invention includes a pre-amplifier stage which comprises two emitter-connected transitors, one of whose bases is supplied with an input signal and an output stage comprising complementary pair of a first transistor of a PNP type and an emitter-grounded second transistor of an NPN type which carry out a class-AB push-pull operation in accordance with the amplitude of a current from the pre-amplifier stage. The power-amplifier circuit of this invention further comprises third transistor for detecting an operating current of the first transistor of the output stage, a fourth transistor which is driven by the third transistor and whose base is connected to the base of the second transistor of the output stage, and fifth and sixth transistors which are connected in such a manner that a sum of the base-emitter voltages of the fifth and sixth transistors is made equal to a sum of the base-emitter voltages of the second and fourth transistors, and through which there flows a current corresponding to a product of the operating currents of the first and second transistors constituting the output stage. A current running through the fifth and sixth transistors is supplied to the pre-amplifier means through a negative feedback path so as to be regulated.

摘要翻译： 体现本发明的功率放大电路包括前置放大器级，其包括两个发射极连接的转换器，其基极之一被提供有输入信号，并且输出级包括PNP型的第一晶体管和发射极 NPN型的接地第二晶体管，其根据来自前置放大器级的电流的幅度进行AB类推挽操作。 本发明的功率放大器电路还包括用于检测输出级的第一晶体管的工作电流的第三晶体管，由第三晶体管驱动的第四晶体管，其基极连接到第二晶体管的基极 输出级和第五和第六晶体管，其以使第五和第六晶体管的基极 - 发射极之和的总和等于第二和第四晶体管的基极 - 发射极电压之和的方式连接，以及 流过与对应于构成输出级的第一和第二晶体管的工作电流的乘积的电流。 通过第五和第六晶体管的电流通过负反馈路径被提供给前置放大器装置，以便被调节。