公开(公告)号：US5904568A

公开(公告)日：1999-05-18

申请号：US941294

申请日：1997-09-30

申请人： Masahiko Maeda ,  Takamitsu Harada ,  Hisami Motoura ,  Eiichi Asano

发明人： Masahiko Maeda ,  Takamitsu Harada ,  Hisami Motoura ,  Eiichi Asano

IPC分类号： H01L21/306 ,  H01L21/302 ,  H01L21/304 ,  H01L21/00 ,  H01L21/02

CPC分类号： H01L21/02008

摘要： A process for precisely and efficiently manufacturing a semiconductor wafer is provided, which can prevent contamination by metals inside silicon crystals and remove the factors that degrade the GOI produced during the wafer manufacturing steps. A sliced and chamfered semiconductor wafer is subjected to lapping. The lapped semiconductor wafer is then etched, and thus the working strains produced by lapping is removed. The two sides of the etched semiconductor wafer are then primary polished with a dual-surface polishing machine. The primary polished semiconductor wafer is etched with an aqueous solution of 1% NaOH solution. The weak alkali etched semiconductor wafer is then mirror processed by a finish polishing. The finish polished semiconductor wafer is washed with an SC-1 solution.

摘要翻译： 提供了精确高效地制造半导体晶片的方法，其可以防止硅晶体内的金属的污染，并消除在晶片制造步骤期间产生的降低GOI的因素。 对切​​割的和倒角的半导体晶片进行研磨。 然后对重叠的半导体晶片进行蚀刻，从而去除通过研磨产生的工作应变。 然后用双面抛光机对蚀刻的半导体晶片的两面进行初级抛光。 用1％NaOH溶液的水溶液蚀刻主抛光的半导体晶片。 然后通过精加工抛光对弱碱蚀刻的半导体晶片进行镜面加工。 精加工的半导体晶片用SC-1溶液洗涤。

公开(公告)号：US5990022A

公开(公告)日：1999-11-23

申请号：US998756

申请日：1997-12-29

申请人： Hisami Motoura ,  Eiichi Asano

发明人： Hisami Motoura ,  Eiichi Asano

IPC分类号： H01L21/66 ,  H01L23/544 ,  H01L21/312

CPC分类号： H01L22/20 ,  H01L22/34 ,  H01L22/12

摘要： The evaluating method includes: dipping a mirror-polished silicon wafer in a dilute hydrofluoric acid; washing the surface of the silicon wafer; subjecting the surface-washed silicon wafer to a heat treatment in an oxygen atmosphere to form a thermal oxidation film; forming a predetermined number of polycrystalline silicon electrodes having a predetermined area on the thermal oxidation film; applying a voltage to each electrode between the predetermined number of polycrystalline silicon electrodes and the silicon wafer; and judging the quality of the mirror-polishing process of the silicon wafers in accordance with the breakdown electric field intensity of the leakage current obtained by measuring the oxide film insulation.

摘要翻译： 评价方法包括：将镜面抛光的硅晶片浸入稀氢氟酸中; 洗涤硅晶片的表面; 使经表面洗涤的硅晶片在氧气氛中进行热处理以形成热氧化膜; 在热氧化膜上形成预定数量的具有预定面积的多晶硅电极; 在预定数量的多晶硅电极和硅晶片之间的每个电极施加电压; 并且根据通过测量氧化膜绝缘获得的漏电流的击穿电场强度判断硅晶片的镜面抛光工艺的质量。

公开(公告)号：US5897327A

公开(公告)日：1999-04-27

申请号：US14084

申请日：1998-01-27

申请人： Eiichi Asano ,  Hisami Motoura ,  Yasuhiro Shimada

发明人： Eiichi Asano ,  Hisami Motoura ,  Yasuhiro Shimada

IPC分类号： G01N27/00 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/12

摘要： A MOS capacitor in which an insulating layer of thermal oxide film is disposed between the electrode 2 and the silicon wafer 1 is formed. While a light beam of an energy larger than 1.1 eV is irradiated on the electrode 2 and its periphery, electrons inject from the electrode 2 side (voltage is applied from the silicon wafer 1 side). The injected electrons are activated by the light irradiation. For both p-type or n-type semiconductor, the dielectric breakdown electric field strength can be precisely measured according to the degree of processing defects. The evaluation method is particularly effective for the n-type semiconductor wafer, which was difficult to evaluate by the prior art.

摘要翻译： 形成在电极2和硅晶片1之间配置有热氧化膜绝缘层的MOS电容器。 虽然能量大于1.1eV的光束照射在电极2及其周围，但电子从电极2侧注入电压（从硅晶片1侧施加电压）。 注入的电子被光照射激活。 对于p型或n型半导体，可以根据加工缺陷的程度精确地测量绝缘击穿电场强度。 该评价方法对于现有技术难以评价的n型半导体晶片特别有效。

公开(公告)号：US5744380A

公开(公告)日：1998-04-28

申请号：US806310

申请日：1997-02-26

申请人： Noriyuki Uemura ,  Hisami Motoura ,  Masashi Nishimura ,  Mitsuo Kohno

发明人： Noriyuki Uemura ,  Hisami Motoura ,  Masashi Nishimura ,  Mitsuo Kohno

IPC分类号： H01L21/66 ,  C23C14/08 ,  C30B13/00 ,  C30B15/00 ,  C30B29/06 ,  G01N21/88

CPC分类号： C30B13/00 ,  C30B15/00 ,  C30B29/06 ,  Y10S117/904 ,  Y10S438/974

摘要： There is provided a high quality epitaxial water on which the density of microscopic defects in the epitaxial layer is reduced to keep the GOI thereof sufficiently high and to reduce a leakage current at the P-N junction thereof when devices are incorporated, to thereby improve the yield of such devices. In an epitaxial wafer obtained by forming an epitaxial layer on a substrate, the density of IR laser scatterers is 5.times.10.sup.5 pieces/cm.sup.3 or less throughout the epitaxial layer.

摘要翻译： 提供了一种高质量的外延水，其中外延层中的微观缺陷密度降低，以保持GOI足够高，并且当装置结合时，其PN结处的漏电流减小，从而提高了产量 这样的设备。 在通过在衬底上形成外延层获得的外延晶片中，IR激光散射体的密度在整个外延层中为5×10 5个/ cm 3以下。

公开(公告)号：US5943549A

公开(公告)日：1999-08-24

申请号：US998757

申请日：1997-12-29

申请人： Hisami Motoura ,  Kouichirou Hayashida

发明人： Hisami Motoura ,  Kouichirou Hayashida

IPC分类号： G01N21/88 ,  G01N21/956 ,  H01L21/304 ,  H01L21/66 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L22/24 ,  G01N21/8803 ,  H01L22/12

摘要： The method of evaluating silicon wafers according to this invention is capable of predicating degradation of the quality of oxide film insulation, which is incurred, on the silicon wafers, by process faults or local residual strains undetectable by the naked eye. The method includes the following steps of: removing selectively a surface of a silicon wafer treated by mirror polishing by using an etching selectivity caused by an unordinary surface state; counting the number of etch pits on the surface of the silicon wafer with the aid of an optical microscope; and judging the quality of the silicon wafer based on the etch pit density, which is calculated from the above number of etch pits, and the threshold value of etch pit density. The threshold value of etch pit density of the silicon wafer treated by selective etching is set to be below 5.times.10.sup.5 pits/cm.sup.2, and improvements to the processing of production lines relating to low-quality silicon wafers can be made.

摘要翻译： 根据本发明的评估硅晶片的方法能够通过不能被肉眼检测到的工艺缺陷或局部残余应变来预测在硅晶片上产生的氧化膜绝缘质量的劣化。 该方法包括以下步骤：通过使用由非常表面状态引起的蚀刻选择性来选择性地去除通过镜面抛光处理的硅晶片的表面; 借助于光学显微镜计数硅晶片表面上的蚀刻凹坑的数量; 以及根据从上述蚀刻凹坑数量计算的蚀刻坑密度和蚀刻坑密度的阈值来判断硅晶片的质量。 通过选择性蚀刻处理的硅晶片的蚀刻坑密度的阈值设定为低于5×10 5个凹坑/ cm 2，并且可以对与低质量硅晶片相关的生产线进行改进。