公开(公告)号：US20130147499A1

公开(公告)日：2013-06-13

申请号：US13316373

申请日：2011-12-09

申请人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

发明人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

IPC分类号： G01R31/00

CPC分类号： G01R31/31924

摘要： A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

摘要翻译： 模式发生器产生表示要提供给DUT的测试信号的模式信号。 驱动器产生具有对应于模式信号的电平的测试信号，并且将如此产生的测试信号输出到DUT。 电压调制器在预定电压范围内改变从驱动器DR输出的测试信号的电压电平。

公开(公告)号：US07834639B2

公开(公告)日：2010-11-16

申请号：US12022162

申请日：2008-01-30

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida

IPC分类号： G01R31/02

CPC分类号： G01R31/31709 ,  H03K3/84 ,  H03K5/156

摘要： Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.

摘要翻译： 提供了一种抖动注入电路，其产生包括抖动的抖动信号，包括并行接收所提供的参考信号的多个延迟电路，并且每个将接收到的参考信号延迟预设的延迟量，以及产生每个边沿的信号产生部分 根据由每个延迟电路输出的信号的定时的抖动信号。 在抖动注入电路中，将至少一个延迟电路的延迟量设定为与抖动信号的平均周期的整数倍不同的值。

公开(公告)号：US20100106468A1

公开(公告)日：2010-04-29

申请号：US12257395

申请日：2008-10-24

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Kiyotaka Ichiyama

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Kiyotaka Ichiyama

IPC分类号： G06F7/60 ,  G06F17/18

CPC分类号： G01R31/31919 ,  G01R29/26 ,  G01R31/2837 ,  G01R31/2894

摘要： There is provided a deterministic component model identifying apparatus for determining a type of a deterministic component contained in a probability density function supplied thereto. The deterministic component model identifying apparatus includes a spectrum calculating section that calculates a spectrum of the probability density function on an axis of a predetermined variable, a null value detecting section that detects a null value on the axis of the predetermined variable in the calculated spectrum, a theoretical value calculating section that calculates a theoretical value of a spectrum of the deterministic component in association with each of a plurality of predetermined deterministic component types, based on the null value detected by the null value detecting section, and a model determining section that determines, as the type of the deterministic component contained in the probability density function, a deterministic component type associated with a logarithmic magnitude spectrum difference most similar to a logarithmic magnitude spectrum of a Gaussian distribution, where the logarithmic magnitude spectrum difference is produced by subtracting the theoretical value of the spectrum of the deterministic component calculated in association with each of the plurality of predetermined deterministic component types from the spectrum calculated by the spectrum calculating section.

摘要翻译： 提供了一种用于确定包含在提供给它的概率密度函数中的确定性分量的类型的确定性分量模型识别装置。 确定性分量模型识别装置包括频谱计算部分，其计算预定变量的轴上的概率密度函数的频谱;空值检测部分，其检测所计算的频谱中的预定变量的轴上的零值; 理论值计算部，基于由空值检测部检测出的空值，与多个预定确定部分类型中的每一个相关联地计算确定性分量的频谱的理论值;以及模型确定部，其确定 ，作为包含在概率密度函数中的确定性分量的类型，与与高斯分布的对数幅度谱最相似的对数幅度谱差相关的确定性分量类型，其中通过减去理论产生对数幅度谱差 根据由频谱计算部分计算的频谱，与多个预定确定性分量类型中的每一个相关联地计算出的确定性分量的频谱的等级值。

公开(公告)号：US20080077342A1

公开(公告)日：2008-03-27

申请号：US11535279

申请日：2006-09-26

申请人： Kiyotaka ICHIYAMA ,  Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Kiyotaka ICHIYAMA ,  Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： There is provided a jitter measurement apparatus for measuring a jitter of a data signal having a substantially constant data rate. The jitter measurement apparatus includes therein a signal converting section that converts the data signal into a clock signal, where the clock signal retains timings of data transition edges of the data signal at which a data value of the data signal transits and has edges whose cycle is substantially equal to the data rate, an analytic signal generating section that converts the clock signal into an analytic signal of a complex number, and a jitter measuring section that measures the jitter of the data signal based on the analytic signal.

摘要翻译： 提供了一种用于测量具有基本上恒定的数据速率的数据信号的抖动的抖动测量装置。 抖动测量装置包括信号转换部分，其将数据信号转换成时钟信号，其中时钟信号保持数据信号的数据值的数据转换边沿的定时，数据信号的数据值在该周期为 基本上等于数据速率，将时钟信号转换为复数分析信号的分析信号生成部分，以及基于分析信号测量数据信号的抖动的抖动测量部分。

公开(公告)号：US20060268970A1

公开(公告)日：2006-11-30

申请号：US11137786

申请日：2005-05-25

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04B3/46

CPC分类号： G01R31/31709

摘要： There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, including a pulse generating section having first pulse generating means for detecting edges of the data-signal-under-measurement to output a first pulse signal having a pulse width set in advance corresponding to the edge and second pulse generating means for detecting boundaries of data sections where data values do not change in the data-signal-under-measurement to output a second pulse signal having a pulse width set in advance over the edge timings of the boundaries of the detected data sections and a jitter calculating section for calculating timing jitter in the data-signal-under-measurement based on the first and second pulse signals.

公开(公告)号：US20060018418A1

公开(公告)日：2006-01-26

申请号：US10896751

申请日：2004-07-22

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H03D3/24

CPC分类号： G01R31/31709 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/3191 ,  G01R31/31937

摘要： A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.

公开(公告)号：US09151801B2

公开(公告)日：2015-10-06

申请号：US13165796

申请日：2011-06-22

申请人： Masahiro Ishida ,  Kiyotaka Ichiyama

发明人： Masahiro Ishida ,  Kiyotaka Ichiyama

IPC分类号： G01R31/319 ,  G01R31/3193 ,  G01R31/317

CPC分类号： G01R31/31932 ,  G01R31/31703 ,  G01R31/31924

摘要： Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level.

摘要翻译： 提供一种测量输入信号的测量电路，包括：电平比较部分，根据测量信号的信号电平与设定的阈值电平之间的比较结果输出逻辑值; 逻辑比较部，其在输入的比较定时获取由所述电平比较部输出的逻辑值; 以及定时调整部，其基于所测量的信号的期望值模式和阈值水平，调整由所述电平比较部输出的信号和所述比较定时的相对相位。

公开(公告)号：US08896332B2

公开(公告)日：2014-11-25

申请号：US13316373

申请日：2011-12-09

申请人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

发明人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

IPC分类号： G01R31/00 ,  G01R31/26

CPC分类号： G01R31/31924

摘要： A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

摘要翻译： 模式发生器产生表示要提供给DUT的测试信号的模式信号。 驱动器产生具有对应于模式信号的电平的测试信号，并且将如此产生的测试信号输出到DUT。 电压调制器在预定电压范围内改变从驱动器DR输出的测试信号的电压电平。

公开(公告)号：US08014465B2

公开(公告)日：2011-09-06

申请号：US12136048

申请日：2008-06-10

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： H04L27/00

CPC分类号： H04L27/365 ,  H03C5/00 ,  H04L27/2092

摘要： Provided is a digital modulator, including a carrier wave output section that outputs a carrier wave, a variable delay section that delays the carrier wave, and a delay amount setting section that sets a delay amount by which the variable delay section delays the carrier wave based on transmission data being transmitted by the carrier wave. The variable delay section may include a multi-stage delay buffer circuit in which delay buffers that delay an input signal by a unit shift amount are connected in a cascade connection, the multi-stage delay buffer circuit may receive the carrier wave at a first-stage delay buffer as input, and the delay amount setting section may include a multiplexer that selects either an output from the carrier wave output section or an output from each stage of the multi-stage delay buffer circuit.

摘要翻译： 提供了一种数字调制器，包括输出载波的载波输出部分，延迟载波的可变延迟部分和设置可变延迟部分延迟载波的延迟量的延迟量设置部分 在由载波发送的发送数据上。 可变延迟部分可以包括多级延迟缓冲电路，其中延迟缓冲器将输入信号延迟单位偏移量连接在级联中，多级延迟缓冲电路可以以第一级延迟缓冲电路接收载波， 延迟量设定部可以包括选择来自载波输出部的输出或多级延迟缓冲电路的各级的输出的多路复用器。

公开(公告)号：US07945405B2

公开(公告)日：2011-05-17

申请号：US12116970

申请日：2008-05-08

申请人： Masahiro Ishida ,  Kiyotaka Ichiyama

发明人： Masahiro Ishida ,  Kiyotaka Ichiyama

IPC分类号： G01R13/00 ,  G06F17/18

CPC分类号： G01R31/31709

摘要： Provided is a jitter measurement apparatus, including a sampling section that samples a signal under measurement having a cycle T, a waveform reconfiguring section that shapes a reconfigured waveform having the cycle T by rearranging ordinal ranks of sample values sampled by the sampling section, a distribution generating section that generates a timing distribution of edges in the reconfigured waveform, and a statistical value calculating section that calculates a statistical value of the timing distribution. The sampling section may sample the signal under measurement having the cycle T a certain number of times N while the signal under measurement repeats for M cycles, where M and N are coprime.

摘要翻译： 提供了一种抖动测量装置，包括：对具有周期T的测量信号进行采样的采样部分;波形重构部分，通过重新排列由采样部分采样的样本值的序列，对具有周期T的重构波形进行整形;分布 生成部，其生成重新配置的波形中的边缘的定时分布;以及统计值计算部，其计算定时分布的统计值。 采样部分可以对具有周期T一定次数N的测量信号进行采样，而测量信号重复M个周期，其中M和N是互质的。