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1.发明授权Microprocessor having an effective BiCMOS extra multiple input complex logic circuit 失效微处理器具有有效的BiCMOS多输入复数逻辑电路
公开(公告)号：US5590361A
公开(公告)日：1996-12-31
申请号：US364406
申请日：1994-12-23
CPC分类号： G06F15/7846 , Y02B60/1225
摘要： An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.
摘要翻译： 使用N（N> / = 2）个单元逻辑电路构造的微处理器中用于执行大量控制和算术运算的额外大量的输入复数逻辑电路，每个单元逻辑电路包括M（M> / = 1）输入CMOS逻辑电路和一个双极晶体管，由此各个输出被集成以响应于M×N个数字输入信号产生一个输出，以提供高速，高密度集成和低功耗微处理器。
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2.发明授权公开(公告)号：US06467004B1
公开(公告)日：2002-10-15
申请号：US09477448
申请日：2000-01-04
IPC分类号： G06F938
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
摘要翻译： 提供了一种高速，高性能流水线半导体器件，例如流水线数据处理设备和存储器件。 在流水线操作中，功能电路单元和传输单元在每个流水线级周期被单独控制。 两个功能电路单元之间的传输单元在考虑周期时间的同时被分成N个传输单元，并且每个划分的传输单元被分配一个流水线级周期。
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公开(公告)号：US6029220A
公开(公告)日：2000-02-22
申请号：US957914
申请日：1992-10-08
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
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4.发明授权Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC
公开(公告)号：US5153452A
公开(公告)日：1992-10-06
申请号：US401849
申请日：1989-08-30
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/56 , H01L21/822 , H01L27/06
CPC分类号： G11C11/565 , G05F1/465 , G11C5/147 , G11C16/30
摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.
摘要翻译： 提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。 内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。 门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。 因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。
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公开(公告)号：US5339448A
公开(公告)日：1994-08-16
申请号：US015296
申请日：1993-01-22
申请人： Shigeya Tanaka , Masahiro Iwamura , Tatsumi Yamauchi , Tatsuo Nojiri , Hisashi Tada , Tetsuo Nakano
发明人： Shigeya Tanaka , Masahiro Iwamura , Tatsumi Yamauchi , Tatsuo Nojiri , Hisashi Tada , Tetsuo Nakano
CPC分类号： G06F13/1684 , G06F13/4027 , G06F13/4072
摘要： A microprocessor according to the present invention comprises a sub-read bus, to which output terminals of registers of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus of the microprocessor through a bus output circuit. Upon occurrence of a read access to any of the registers, the bus output circuit couples the sub-read bus with the main read bus, whereby data read out from the registers to the sub-read bus are transmitted to the main read bus, and under no existence of the read access, the bus output circuit interrupts the data transmission from the sub-read bus to the main read bus. With this, a load capacitance of the read bus is reduced. As a result, a time for making access to the read bus is much improved.
摘要翻译： 根据本发明的微处理器包括子读总线，微处理器的寄存器文件的寄存器的输出端耦合到该子读总线。 子读取总线又通过总线输出电路耦合到微处理器的主读取总线。 在发生对任何寄存器的读取访问时，总线输出电路将子读总线与主读总线耦合，由此从寄存器读出到子读总线的数据被发送到主读总线， 在不存在读访问的情况下，总线输出电路中断从子读总线到主读总线的数据传输。 因此，读总线的负载电容减小。 结果，访问读总线的时间大大改善。
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6.发明授权Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件公开(公告)号：US06675311B2
公开(公告)日：2004-01-06
申请号：US10002444
申请日：2001-12-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F104
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.
摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件。 至少一对逻辑设备由时钟信号K1同步控制。
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公开(公告)号：US6088808A
公开(公告)日：2000-07-11
申请号：US966972
申请日：1997-11-10
申请人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
IPC分类号： G06F1/32 , B60Q1/44 , G06F1/26 , G06F9/34 , G06F9/38 , G06F15/78 , G11C11/417 , G11C11/419
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3287 , G06F15/7832 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3859 , G06F9/3869 , G06F9/3885 , G11C11/417 , G11C11/419 , Y02B60/1282 , Y02B60/32
摘要： In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
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公开(公告)号：US5457790A
公开(公告)日：1995-10-10
申请号：US136990
申请日：1993-10-18
申请人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Hideo Maejima , Tetsuo Nakano
IPC分类号： G06F1/32 , B60Q1/44 , G06F1/26 , G06F9/34 , G06F9/38 , G06F15/78 , G11C11/417 , G11C11/419
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3287 , G06F15/7832 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3859 , G06F9/3869 , G06F9/3885 , G11C11/417 , G11C11/419 , Y02B60/1282 , Y02B60/32
摘要： In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.
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9.发明授权Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 失效根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
公开(公告)号：US5968160A
公开(公告)日：1999-10-19
申请号：US923632
申请日：1997-09-04
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。
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公开(公告)号：US5506982A
公开(公告)日：1996-04-09
申请号：US278245
申请日：1994-07-21
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
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