公开(公告)号：US20110104852A1

公开(公告)日：2011-05-05

申请号：US13005350

申请日：2011-01-12

申请人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US08513121B2

公开(公告)日：2013-08-20

申请号：US13621134

申请日：2012-09-15

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

公开(公告)号：US07893540B2

公开(公告)日：2011-02-22

申请号：US12537723

申请日：2009-08-07

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US08298940B2

公开(公告)日：2012-10-30

申请号：US13005350

申请日：2011-01-12

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US20070001281A1

公开(公告)日：2007-01-04

申请号：US11476145

申请日：2006-06-28

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US20130011967A1

公开(公告)日：2013-01-10

申请号：US13621134

申请日：2012-09-15

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

公开(公告)号：US07576433B2

公开(公告)日：2009-08-18

申请号：US11476145

申请日：2006-06-28

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US07489030B2

公开(公告)日：2009-02-10

申请号：US11635500

申请日：2006-12-08

申请人： Kayoko Shibata ,  Hiroaki Ikeda ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

发明人： Kayoko Shibata ,  Hiroaki Ikeda ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  G11C5/04 ,  G11C29/02 ,  G11C29/022 ,  G11C29/70 ,  H01L21/485 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.

摘要翻译： 作为有缺陷的接触恢复元件，堆叠半导体器件包括其中信号路径被复用的并行布置系统，以及可操作以将信号路径切换到辅助信号路径的缺陷接触恢复电路。 在串行数据传输的情况下，使用并行布置系统，并且需要非常高速的操作。 在由于并行数据传送而导致信号数量大的情况下使用有缺陷接触恢复电路。

公开(公告)号：US20070117317A1

公开(公告)日：2007-05-24

申请号：US11560898

申请日：2006-11-17

申请人： Hiroaki Ikeda ,  Kayoko Shibata ,  Junji Yamada

发明人： Hiroaki Ikeda ,  Kayoko Shibata ,  Junji Yamada

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： G11C5/025

摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.

摘要翻译： 在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。 堆叠存储器包括存储器核心层，插入器和IF芯片。 通过堆叠具有相同布置的存储器核心层，可以处理无视操作和奇偶校验操作两者。 此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。 此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。 这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

公开(公告)号：US08907463B2

公开(公告)日：2014-12-09

申请号：US13094214

申请日：2011-04-26

申请人： Kayoko Shibata ,  Hiroaki Ikeda

发明人： Kayoko Shibata ,  Hiroaki Ikeda

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/535 ,  H01L23/544

CPC分类号： G11C11/407 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5444 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

摘要翻译： 公开了一种包括多个半导体芯片和多个通线组的半导体器件。 每个通线组由唯一数量的通线组成。 与通过线组相关联的数字彼此互为互补。 当对于每条直线组选择其中一根直线时，半导体芯片中的一个通过多条通线组中所选择的直通线的组合来指定。