公开(公告)号：US08716746B2

公开(公告)日：2014-05-06

申请号：US13205845

申请日：2011-08-09

申请人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

发明人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

IPC分类号： H01L29/66

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

摘要： In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

摘要翻译： 在半导体装置中，IGBT单元包括通过半导体衬底的基底层到半导体衬底的漂移层的沟槽，沟槽内表面上的栅极绝缘膜，栅极绝缘膜上的栅电极， 在基底层的表面部分中的第一导电型发射极区域和在基底层的表面部分中的第二导电类型的第一接触区域。 IGBT单元还包括设置在基极层内的第一导电型浮动层，以将基极层分离成包括发射极区域和第一接触区域的第一部分和与漂移层相邻的第二部分，以及层间绝缘膜 设置成覆盖栅电极的端部。 二极管单元在基层的表面部分包括第二导电类型的第二接触区域。

公开(公告)号：US20120043581A1

公开(公告)日：2012-02-23

申请号：US13205845

申请日：2011-08-09

申请人： Masaki KOYAMA ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

发明人： Masaki KOYAMA ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

IPC分类号： H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

摘要： In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

摘要翻译： 在半导体装置中，IGBT单元包括通过半导体衬底的基底层到半导体衬底的漂移层的沟槽，沟槽内表面上的栅极绝缘膜，栅极绝缘膜上的栅电极， 在基底层的表面部分中的第一导电型发射极区域和在基底层的表面部分中的第二导电类型的第一接触区域。 IGBT单元还包括设置在基极层内的第一导电型浮动层，以将基极层分离成包括发射极区域和第一接触区域的第一部分和与漂移层相邻的第二部分，以及层间绝缘膜 设置成覆盖栅电极的端部。 二极管单元在基层的表面部分包括第二导电类型的第二接触区域。

公开(公告)号：US08952449B2

公开(公告)日：2015-02-10

申请号：US13210624

申请日：2011-08-16

申请人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

发明人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

IPC分类号： H01L29/06 ,  H01L29/861 ,  H01L21/263 ,  H01L21/266 ,  H01L29/08 ,  H01L29/32 ,  H01L29/739 ,  H01L21/265

CPC分类号： H01L29/8611 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/063 ,  H01L29/0834 ,  H01L29/32 ,  H01L29/7397

摘要： There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.

摘要翻译： 已知在IGBT区域中设置IGBT结构并且在二极管区域中设置二极管结构的IGBT半导体器件，IGBT面积和二极管面积都位于同一衬底内，并且IGBT区域与 二极管面积。 在这种类型的半导体器件中，当IGBT结构关断时，积聚在IGBT区域内的载流子流入二极管区域的现象。 为了防止这种现象，至少在所述IGBT区域内并与所述二极管区域相邻的子区域中提供载流子缩短寿命的区域。 在子区域中，省略了IGBT结构的发射极。

公开(公告)号：US20100276729A1

公开(公告)日：2010-11-04

申请号：US12743525

申请日：2008-12-02

申请人： Sachiko Aoi ,  Takahide Sugiyama ,  Takashi Suzuki ,  Akitaka Soeno ,  Tsuyoshi Nishiwaki

发明人： Sachiko Aoi ,  Takahide Sugiyama ,  Takashi Suzuki ,  Akitaka Soeno ,  Tsuyoshi Nishiwaki

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66348 ,  H01L29/66734

摘要： IGBT 10 comprises an n+-type emitter region, an n−-type drift region, a p-type body region disposed between the emitter region and the drift region, a trench gate extending in the body region from the emitter region toward the drift region, and a projecting portion of an insulating material being in contact with a surface of the trench gate. At least a part of the projecting portion projects within the drift region.

摘要翻译： IGBT10包括n +型发射极区域，n型漂移区域，设置在发射极区域和漂移区域之间的p型体区域，在体区域中从发射极区域延伸到漂移区域的沟槽栅极 并且绝缘材料的突出部分与沟槽栅极的表面接触。 突出部分的至少一部分在漂移区域内突出。

公开(公告)号：US09024330B2

公开(公告)日：2015-05-05

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

发明人： Yukihiko Watanabe ,  Sachiko Aoi ,  Masahiro Sugimoto ,  Akitaka Soeno ,  Shinichiro Miyahara

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US09640651B2

公开(公告)日：2017-05-02

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

IPC分类号： H01L29/94 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

公开(公告)号：US08299496B2

公开(公告)日：2012-10-30

申请号：US13242960

申请日：2011-09-23

申请人： Tatsuji Nagaoka ,  Akitaka Soeno

发明人： Tatsuji Nagaoka ,  Akitaka Soeno

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L21/761 ,  H01L27/0727 ,  H01L29/32 ,  H01L29/7397 ,  H01L29/861

摘要： Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

摘要翻译： 提供一种半导体器件，其包括其中形成二极管区域和IGBT区域的半导体衬底。 在二极管区域和IGBT区域之间的范围内形成由p型半导体形成的分离区域，并且从半导体衬底的上表面延伸到比阳极区域和下端部的下端更深的位置 的身体区域。 二极管寿命控制区形成在二极管漂移区内。 二极管寿命控制区域中的载流子寿命短于二极管寿命控制区域外的二极管漂移区域中的载流子寿命。 IGBT区域侧的二极管寿命控制区域的一端位于分离区域正下方。

公开(公告)号：US20140077253A1

公开(公告)日：2014-03-20

申请号：US13695749

申请日：2011-06-08

申请人： Akitaka Soeno

发明人： Akitaka Soeno

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/32 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device includes a drift layer formed in a semiconductor substrate, and a body layer formed at an upper surface of the semiconductor substrate and located on an upper surface side of the drift layer. The drift layer includes a lifetime control region having a crystal defect density that is equal to or higher than h/2, where h is a maximum value of a crystal defect density of the drift layer that varies in a depth direction of the semiconductor substrate. The lifetime control region is formed by irradiating charged particles to a first conductivity type pre-drift layer including a first resistance layer and a second resistance layer, a resistivity of the second resistance layer being lower than a resistivity of the first resistance layer. At least of a part of the lifetime control region is formed in a range of the second resistance layer.

摘要翻译： 半导体器件包括形成在半导体衬底中的漂移层和形成在半导体衬底的上表面并位于漂移层的上表面侧的体层。 漂移层包括具有等于或高于h / 2的晶体缺陷密度的寿命控制区，其中h是在半导体衬底的深度方向上变化的漂移层的晶体缺陷密度的最大值。 寿命控制区域通过将带电粒子照射到包括第一电阻层和第二电阻层的第一导电型预漂移层而形成，第二电阻层的电阻率低于第一电阻层的电阻率。 寿命控制区域的至少一部分形成在第二电阻层的范围内。

公开(公告)号：US08384211B2

公开(公告)日：2013-02-26

申请号：US12990681

申请日：2009-04-30

申请人： Akitaka Soeno

发明人： Akitaka Soeno

IPC分类号： H01L23/10

CPC分类号： H01L23/473 ,  H01L23/3735 ,  H01L24/34 ,  H01L25/072 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated.

摘要翻译： 半导体装置依次包括：第一层叠体，其包括第一散热板，第一绝缘层，第一导电层和第一半导体元件; 包括第二散热板，第二绝缘层，第二导电层和第二半导体元件的第二堆叠体，并且构造成由与第一半导体元件不同的半导体材料制成; 以及连接部，被配置为电连接所述第一导电层和所述第二导电层，其中所述第一层叠体和所述第二层叠体是绝热的。

公开(公告)号：US20100283514A1

公开(公告)日：2010-11-11

申请号：US12677131

申请日：2008-08-28

申请人： Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

发明人： Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC分类号： G05F3/02

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H03K17/08128 ,  H03K17/0828

摘要： In a reverse conducting semiconductor device, which forms a composition circuit, a positive voltage that is higher than a positive voltage of a collector electrode may be applied to an emitter electrode. In this case, in a region of the reverse conducting semiconductor device in which a return diode is formed, a body contact region functions as an anode, a drift contact region functions as a cathode, and current flows from the anode to the cathode. When a voltage having a lower electric potential than the collector electrode is applied to the trench gate electrode at that time, p-type carriers are generated within the cathode and a quantity of carriers increases within the return diode. As a result, a forward voltage drop of the return diode lowers, and constant loss of electric power can be reduced. Electric power loss can be reduced in a power supply device that uses such a composition circuit in which a switching element and the return diode are connected in reverse parallel.

摘要翻译： 在形成合成电路的反向导通半导体器件中，可以将高于集电极的正电压的正电压施加到发射极。 在这种情况下，在形成有返回二极管的反向导通半导体器件的区域中，体接触区域用作阳极，漂移接触区域用作阴极，并且电流从阳极流到阴极。 此时当沟槽栅电极施加具有比集电极电位低的电压的电压时，在阴极内产生p型载流子，在返回二极管内增加载流子数量。 结果，返回二极管的正向压降降低，并且可以减少电力的恒定损失。 在使用其中开关元件和返回二极管反向并联连接的组合电路的电源装置中，电力损耗可以减小。