公开(公告)号：US4719597A

公开(公告)日：1988-01-12

申请号：US766279

申请日：1985-08-16

申请人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

发明人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/06

摘要： A cut-off clock .phi..sub.5 generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock .phi..sub.5 to produce two types of cut-off clocks .phi..sub.5L and .phi..sub.5R. The two types of cut-off clocks .phi..sub.5L and .phi..sub.5R are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks .phi..sub.2L and .phi..sub.2R. The control clocks .phi..sub.2L and .phi..sub.2R are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7.sub.L, 8.sub.L, 7.sub.R and 8.sub.R.

摘要翻译： 由截止时钟产生电路PG产生的截止时钟phi 5被提供给解码电路DEC。 解码电路DEC解码截止时钟phi 5以产生两种类型的截止时钟phi 5L和phi 5R。 两种类型的截止时钟phi 5L和phi 5R被提供给如图5所示的控制时​​钟产生电路。 3或11，其又产生控制时钟phi 2L和phi 2R。 控制时钟phi 2L和phi 2R被提供给图1的共享读出放大器。 以控制传输晶体管7L，8L，7R和8R的导通截止操作。

公开(公告)号：US4736343A

公开(公告)日：1988-04-05

申请号：US929370

申请日：1986-11-12

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： 44Gate potentials of transistors Q.sub.R0 and Q.sub.R1 provided in an active pull-up circuit APo are always controlled to be appropriate values by a clock signal .phi..sub.p. As a result, reverse flow of electric charge from a capacitor C.sub.R0 or C.sub.R1 to a bit line LB or BL can be prevented and unfavorable influence due to such reverse flow of electric charge can be avoided in operation of the active pull-up circuit APo.

摘要翻译： 在主动上拉电路APo中提供的晶体管QR0和QR1的栅极电位总是通过时钟信号phi被控制为适当的值。 结果，可以防止从电容器CR0或CR1到位线LB或＆amp; upbar＆B的电荷的反向流动，并且在有源上拉电路APo的操作中可以避免由于这种反向电荷的不利影响 。

公开(公告)号：US4730320A

公开(公告)日：1988-03-08

申请号：US825869

申请日：1986-02-04

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC分类号： G06F11/10 ,  G06F11/267

CPC分类号： G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.

摘要翻译： 半导体存储器件包括连接在写入校验位产生电路（2）的输出侧和校验位存储单元阵列（32）的输入侧之间的数据输入切换电路（20），数据输出切换电路（30） ）和连接到地址解码器（9）的输出侧的地址切换电路（10）。 当输入测试模式时，数据输入切换电路（2），数据输出切换电路（30）和地址切换电路（10）连接数据输入信号线（l），数据输出信号线（m）和地址信号 （n）分配给校验位存储单元阵列（32），从而能够从外部访问校验位存储单元阵列（32）。

公开(公告)号：USRE34463E

公开(公告)日：1993-11-30

申请号：US662663

申请日：1991-02-28

申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC分类号： G11C11/4076 ,  G11C11/4094 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

公开(公告)号：US4903268A

公开(公告)日：1990-02-20

申请号：US161890

申请日：1988-02-29

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC分类号： H01L27/10 ,  G06F11/10 ,  G06F11/267 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory comprises a data bit memory cell array (3), a check bit memory cell array (4), and an address decoder (19) which includes a switching circuit (20) for selectively accessing data from either the memory cell array (3) or (4). Decoding signals d.sub.l to d.sub.m are used for reading out data latched by a column address strobe (CAS) signal. The decoding signals are applied to either the memory cell array (3) or (4) through a group of switching elements selectively rendered conductive by complementary signals .phi. and .phi.. The logical values of the signals .phi. and .phi. change responsive to a change in the CAS signal state.

摘要翻译： 半导体存储器包括数据位存储单元阵列（3），校验位存储单元阵列（4）和地址解码器（19），其包括用于选择性地从存储单元阵列中存​​取数据的切换电路（20） 3）或（4）。 解码信号d1至dm用于读出由列地址选通（CAS）信号锁存的数据。 通过互补信号phi和phi选择性地导通的一组开关元件将解码信号施加到存储单元阵列（3）或（4）。 信号phi和phi的逻辑值响应于CAS信号状态的变化而改变。

公开(公告)号：US4734890A

公开(公告)日：1988-03-29

申请号：US929369

申请日：1986-11-12

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4099 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C11/4099 ,  G11C11/4087

摘要： A dynamic RAM has dummy capacitors (C6, C7) having the same capacitance as a memory capacitor connected to a pair of bit lines (BL1, BL1), respectively. During an active period, respective dummy capacitors (C6, C7) are charged to the H level and L level, which are signal levels of the bit lines (BL1, BL1) and during precharge period, both dummy capacitors are equalized. Since both dummy capacitors (C6, C7) respectively connected to a pair of bit lines (BL1, BL1) are equalized during precharge period, so that the stored charge values of the dummy capacitors (C6, C7) both become the intermediate value of the ground level and supply potential level.

摘要翻译： 动态RAM分别具有与连接到一对位线（BL1，＆amp;上升和下降B1）的存储电容器相同的电容的虚拟电容器（C6，C7）。 在有效期间，将各个虚拟电容器（C6，C7）充电为位电平（BL1，上升和下降B1）的信号电平的H电平和L电平，并且在预充电期间，两个虚拟电容器被均衡。 由于分别连接到一对位线（BL1，＆lt;上升＆amp; B1）的两个虚拟电容器（C6，C7）在预充电期间均衡，所以虚拟电容器（C6，C7）的存储的电荷值均成为 地面水平和供应潜力水平。

公开(公告)号：US4675850A

公开(公告)日：1987-06-23

申请号：US748722

申请日：1985-06-25

申请人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

发明人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1045

摘要： A semiconductor memory device is operable selectively in a page mode or a nibble mode, depending upon an external mode selection signal. In the page mode of operation a row address is supplied to the memory with subsequently supplied column addresses corresponding on a one-to-one basis with data to be stored into or read from memory. In the nibble mode of operation, the memory sequentially reads from or writes to four adjacent memory cells for each column address supplied.

摘要翻译： 取决于外部模式选择信号，半导体存储器件可以以页模式或半字节模式选择性地工作。 在页面操作模式中，将行地址提供给存储器，其中随后提供的列地址与要存储到存储器或从存储器读取的数据一一对应。 在半字节操作模式中，存储器对于提供的每个列地址顺序地读取或向四个相邻存储器单元写入。

公开(公告)号：US4896297A

公开(公告)日：1990-01-23

申请号：US112034

申请日：1987-10-23

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

摘要翻译： 一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于 当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

公开(公告)号：US4760559A

公开(公告)日：1988-07-26

申请号：US883311

申请日：1986-07-08

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/4085

摘要： A dynamic type MOS-RAM constructed of folded type bit lines and having sense operation cycles for amplifying potential difference appearing on respective pairs of bit lines after selection of a word line and restore operation cycles for further amplifying the potential difference on the pairs of bit lines after the sense operation cycles, wherein non-selected word lines are completely brought into electrically floating states in intervals including the sense operation cycles and the restore operation cycles.

摘要翻译： 由折叠型位线构成的具有读出操作周期的动态型MOS-RAM，用于放大在选择字线之后出现在各对位线上的电位差，并且还原操作周期用于进一步放大位线对上的电位差 在感测操作周期之后，其中未选择的字线在包括感测操作周期和恢复操作周期的间隔中完全进入电浮动状态。

公开(公告)号：US4692901A

公开(公告)日：1987-09-08

申请号：US762632

申请日：1985-08-05

申请人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

发明人： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

IPC分类号： G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

摘要翻译： 半导体存储器包括存储单元（15-18,27-30），数据写入端（1），数据读出端（48），晶体管（3-10,35-42），地址信号输入端（23- 26），子代码信号输入端子（43-46），驱动信号发生电路（49-52），并行读出电路（79-82）和测试模式切换信号输入端子（53,88）。 在写入存储单元的功能测试数据时，驱动信号发生电路响应于测试模式切换信号而使所有晶体管（3-10）响应于地址信号，从而同时将数据写入存储器 细胞（15-18）。 此外，在读出存储单元的功能测试数据时，并行读出电路响应于不考虑子代码信号的测试模式切换信号读取存储测试数据的存储单元（27-30）的存储内容。 可以提供逻辑电路装置（90,91,94）以当测试数据的所有逻辑值处于相同电平时输出与存储在存储单元中的测试数据相对应的逻辑值。