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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5038191A

    公开(公告)日：1991-08-06

    申请号：US486842

    申请日：1990-03-01

    申请人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/404 ,  G11C11/411 ,  G11C11/412 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/102 ,  H01L29/73 ,  H01L29/732

    CPC分类号： G11C11/4113 ,  G11C11/404 ,  G11C11/412

    摘要： A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.

    摘要翻译： 半导体存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，排列成列的多个字线和排成行的多个位线。 每个存储单元包括双极晶体管，其中控制集电极 - 发射极电压，使得基极电流变化的极性根据基极 - 发射极电压的增加而改变，并且开关元件设置在基极 双极晶体管和相关联的位线，并且可由相关联的字线控制。 提供一种开关电路，用于在第二状态下将集电极电压施加到双极晶体管的集电极，在第二状态下，相关联的一个存储单元保持数据而不是相关联的存储单元可访问用于数据读取和数据的第二状态 写作。

    Semiconductor memory device having register groups for writing and reading data
    6.
    发明授权
    Semiconductor memory device having register groups for writing and reading data 失效
    具有用于写入和读取数据的寄存器组的半导体存储器件

    公开(公告)号：US5467303A

    公开(公告)日：1995-11-14

    申请号：US380443

    申请日：1995-01-30

    申请人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/405 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/404

    摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.

    摘要翻译： 半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到 对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5615163A

    公开(公告)日：1997-03-25

    申请号：US598706

    申请日：1996-02-08

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5715192A

    公开(公告)日：1998-02-03

    申请号：US502947

    申请日：1995-07-17

    申请人： Takehiro Hasegawa ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/40 ,  G11C11/412 ,  G11C11/34

    CPC分类号： G11C11/40 ,  G11C11/412

    摘要： A plurality of static memory cells including CMOS flip-flops and switching MOS transistors are connected in series, thereby forming a memory cell unit in which one end of data reading is connected to bit lines. A series of the memory cell units are arranged, thereby forming a memory cell array. Reset terminals are provided for releasing cell data and causing the cell to function temporarily as a transfer gate of data.

    摘要翻译： 包括CMOS触发器和开关MOS晶体管的多个静态存储单元串联连接，从而形成其中数据读取的一端连接到位线的存储单元单元。 布置一系列存储单元单元，从而形成存储单元阵列。 提供复位端子用于释放单元数据并使单元临时工作作为数据传输门。