公开(公告)号：US5544122A

公开(公告)日：1996-08-06

申请号：US246267

申请日：1994-05-19

申请人： Masao Mizukami ,  Yoichi Sato ,  Satoshi Shinagawa ,  Yukio Nakano

发明人： Masao Mizukami ,  Yoichi Sato ,  Satoshi Shinagawa ,  Yukio Nakano

IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.

摘要翻译： 写列选择存储单元MC的MOSFET与例如电路的地电位耦合。 根据列选择地址信号和写入数据选择性地形成提供给这些MOSFET的写入列选择信号。 因此，存储单元MC的写入列选择MOSFET用作实质的写入装置。 也就是说，写列选择信号线被同时用作数据线。

公开(公告)号：US5422858A

公开(公告)日：1995-06-06

申请号：US260894

申请日：1994-06-16

申请人： Masao Mizukami ,  Yoichi Sato ,  Takahiko Kozaki ,  Satoshi Shinagawa

发明人： Masao Mizukami ,  Yoichi Sato ,  Takahiko Kozaki ,  Satoshi Shinagawa

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F15/78 ,  G11C8/16 ,  G11C11/401 ,  G11C11/407 ,  G11C11/41 ,  G11C8/00

CPC分类号： G11C8/16

摘要： A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

摘要翻译： 速率转换电路区域（8）设置在与时钟信号CLK同步操作的扩展门区域（4）和与时钟信号（ck）同步操作的RAM核心（7）（宏小区）之间。 高于时钟信号（CLK）。 通过这种布置，单端口核心可通过形成时钟信号（ck）作为双端口RAM访问，时钟信号（ck）的频率与时钟信号（CLK）的可选次数相乘，接收访问数据等同于多个 在扩展门区域中的预定单元操作访问周期期间从扩展门区域并行地操作周期，并且在与时钟信号（ck）同步的多个操作周期期间将它们串行提供给RAM核心7。

公开(公告)号：US5359572A

公开(公告)日：1994-10-25

申请号：US872841

申请日：1992-04-23

申请人： Yoichi Sato ,  Satoshi Shinagawa ,  Masao Mizukami

发明人： Yoichi Sato ,  Satoshi Shinagawa ,  Masao Mizukami

IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C11/419 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

摘要： A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

摘要翻译： 静态RAM等的存储器阵列被分割成字线延伸方向以构成多个子存储器阵列SM0至SM7，以及用于选择子存储器阵列的阵列选择信号和用于选择子字的子字线选择信号 线被组合以选择性地形成字线选择信号。 用于发送这些字线信号的主字线M0000至M0003与子字线SW000至SW255并联布置。 子字线驱动电路SWD000〜SWD255还通过组合至少2位的字线选择信号而耦合到各个子字线，以使相应的子字线选择性地选择成选定的状态。

公开(公告)号：US5264744A

公开(公告)日：1993-11-23

申请号：US843214

申请日：1992-02-28

申请人： Masao Mizukami ,  Yoichi Sato

发明人： Masao Mizukami ,  Yoichi Sato

IPC分类号： H03K19/0185 ,  H04L25/08 ,  H03K19/0175 ,  H03K17/16

CPC分类号： H03K19/018514 ,  H04L25/08

摘要： A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

摘要翻译： 信号传输电路，其中信号被转换成从串联电阻器从信号传输电路输出的两个互补信号。 互补信号的幅度由设置在信号接收侧的串联电阻和终端电阻减小。 信号接收侧移动其输入的信号的电平。 电平移位信号由高输入阻抗差分放大电路放大。

公开(公告)号：US4984204A

公开(公告)日：1991-01-08

申请号：US303472

申请日：1989-01-30

申请人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

发明人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

IPC分类号： G11C7/06 ,  G11C8/16

CPC分类号： G11C7/062 ,  G11C8/16

摘要： A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted output to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

摘要翻译： 半导体存储器件具有读出放大器，该读出放大器由具有输入的电平移位电路构成，该输入检测从初始预充电电平到数据线附近的电平变化附近的数据线对应于来自 在存储器的操作的读取模式期间的存储器单元。 电平移位电路响应于存储器单元读取信号，向差分读出放大器电路的输入端提供电平移位输出，电平移位输出位于差分读出放大器电路的工作点附近。 电平移位电路包括具有由电流放大晶体管和电流源的串联连接节点形成的输出端子的电流放大器。

公开(公告)号：US4984201A

公开(公告)日：1991-01-08

申请号：US465983

申请日：1990-01-16

申请人： Yoichi Sato ,  Masao Mizukami

发明人： Yoichi Sato ,  Masao Mizukami

IPC分类号： G11C11/412 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/41 ,  G11C11/413

摘要： Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are precharged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory.

摘要翻译： 存储器阵列的每个存储单元具有用于存储信息的锁存电路，例如一对交叉连接的CMOS反相器，栅极与字线连接的第一开关MOSFET，以及串联连接的第二开关MOSFET 其中第一开关MOSFET和其栅极与锁存电路的输出端相连。 第一和第二开关MOSFET耦合在数据线和提供有第一电源电压电平（例如参考地电位）的端子之间。 这样的存储单元设置在多条数据线和多条字线的交点处。 多个数据线中的一个通过列开关与公共数据线连接，该列开关被替代地进入ON状态。 在读取操作之前，数据线被预先充电到第一电源电压电平或地电位，并且公共数据线被预充电到诸如存储器的电源电压的第二电源电压电平。

公开(公告)号：US5065363A

公开(公告)日：1991-11-12

申请号：US637809

申请日：1991-01-07

申请人： Yoichi Sato ,  Masao Mizukami

发明人： Yoichi Sato ,  Masao Mizukami

IPC分类号： G11C11/412 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/41 ,  G11C11/413

摘要： Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.

摘要翻译： 存储器阵列的每个存储单元具有用于存储信息的锁存电路，例如一对交叉连接的CMOS反相器，栅极与字线连接的第一开关MOSFET，以及串联连接的第二开关MOSFET 其中第一开关MOSFET和其栅极与锁存电路的输出端相连。 第一和第二开关MOSFET耦合在数据线和提供有第一电源电压电平（例如参考地电位）的端子之间。 这样的存储单元设置在多条数据线和多条字线的交点处。 多个数据线中的一个通过列开关与公共数据线连接，该列开关被替代地进入ON状态。 在读取操作之前，数据线被改变为第一电源电压电平或地电位，并且公共数据线被预充电到诸如存储器的电源电压的第二电源电压电平。 存储器阵列实现在诸如静态RAM的半导体存储设备中，其被表征为作为单端口或双端口系统操作，并且其中其还采用写放大器电路布置和读出放大器布置 ，例如单端差分型，其中写入和读出放大器布置可以设置在单独的公共数据线上或在单个公共数据线上。

公开(公告)号：US5053652A

公开(公告)日：1991-10-01

申请号：US637591

申请日：1991-01-04

申请人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

发明人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

IPC分类号： G11C7/06 ,  G11C8/16

CPC分类号： G11C7/062 ,  G11C8/16

摘要： A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

摘要翻译： 半导体存储器件具有读出放大器，该读出放大器由具有输入的电平移位电路构成，该输入检测从初始预充电电平到数据线附近的电平变化附近的数据线对应于来自 在存储器的操作的读取模式期间的存储器单元。 电平移位电路响应于存储单元读取信号，向差分读出放大器电路的输入端提供电平偏移输出，电平移位输出位于差分读出放大器电路的工作点附近。 电平移位电路包括具有由电流放大晶体管和电流源的串联连接节点形成的输出端子的电流放大器。

公开(公告)号：US5111080A

公开(公告)日：1992-05-05

申请号：US614071

申请日：1990-11-13

申请人： Masao Mizukami ,  Yoichi Sato

发明人： Masao Mizukami ,  Yoichi Sato

IPC分类号： G11C11/401 ,  G11C11/409 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/08

CPC分类号： H03K19/018514 ,  H04L25/08

摘要： A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

摘要翻译： 信号传输电路，其中信号被转换成从串联电阻器从信号传输电路输出的两个互补信号。 互补信号的幅度由设置在信号接收侧的串联电阻和终端电阻减小。 信号接收侧移动其输入的信号的电平。 电平移位信号由高输入阻抗差分放大电路放大。

公开(公告)号：US4951259A

公开(公告)日：1990-08-21

申请号：US156742

申请日：1988-02-18

申请人： Yoichi Sato ,  Satoshi Shinagawa

发明人： Yoichi Sato ,  Satoshi Shinagawa

IPC分类号： G11C11/413 ,  G11C8/08

CPC分类号： G11C8/08

摘要： A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.

摘要翻译： 提供一种半导体存储器件，其包括耦合到字线驱动器的输入的多个字线驱动器和逻辑解码电路。 在大存储器阵列中，由于字线驱动器晶体管必须相对较大，所以字线驱动电路可以在逻辑解码电路的输出上放置大的电容性负载。 逻辑解码电路上的这种大负载不利地影响存储器的操作速度。 因此，为了减小该负载，在逻辑解码电路的输出和字线驱动器之间提供切换装置。 可以根据预解码器的控制输出信号来控制该切换装置，以将逻辑解码电路的输出分别连接到字线驱动器。 还可以提供复位MOSFET以防止字线驱动器的输入浮动。