公开(公告)号：US5544122A

公开(公告)日：1996-08-06

申请号：US246267

申请日：1994-05-19

申请人： Masao Mizukami ,  Yoichi Sato ,  Satoshi Shinagawa ,  Yukio Nakano

发明人： Masao Mizukami ,  Yoichi Sato ,  Satoshi Shinagawa ,  Yukio Nakano

IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.

摘要翻译： 写列选择存储单元MC的MOSFET与例如电路的地电位耦合。 根据列选择地址信号和写入数据选择性地形成提供给这些MOSFET的写入列选择信号。 因此，存储单元MC的写入列选择MOSFET用作实质的写入装置。 也就是说，写列选择信号线被同时用作数据线。

公开(公告)号：US5422858A

公开(公告)日：1995-06-06

申请号：US260894

申请日：1994-06-16

申请人： Masao Mizukami ,  Yoichi Sato ,  Takahiko Kozaki ,  Satoshi Shinagawa

发明人： Masao Mizukami ,  Yoichi Sato ,  Takahiko Kozaki ,  Satoshi Shinagawa

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F15/78 ,  G11C8/16 ,  G11C11/401 ,  G11C11/407 ,  G11C11/41 ,  G11C8/00

CPC分类号： G11C8/16

摘要： A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

摘要翻译： 速率转换电路区域（8）设置在与时钟信号CLK同步操作的扩展门区域（4）和与时钟信号（ck）同步操作的RAM核心（7）（宏小区）之间。 高于时钟信号（CLK）。 通过这种布置，单端口核心可通过形成时钟信号（ck）作为双端口RAM访问，时钟信号（ck）的频率与时钟信号（CLK）的可选次数相乘，接收访问数据等同于多个 在扩展门区域中的预定单元操作访问周期期间从扩展门区域并行地操作周期，并且在与时钟信号（ck）同步的多个操作周期期间将它们串行提供给RAM核心7。

公开(公告)号：US5359572A

公开(公告)日：1994-10-25

申请号：US872841

申请日：1992-04-23

申请人： Yoichi Sato ,  Satoshi Shinagawa ,  Masao Mizukami

发明人： Yoichi Sato ,  Satoshi Shinagawa ,  Masao Mizukami

IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C11/419 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

摘要： A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

摘要翻译： 静态RAM等的存储器阵列被分割成字线延伸方向以构成多个子存储器阵列SM0至SM7，以及用于选择子存储器阵列的阵列选择信号和用于选择子字的子字线选择信号 线被组合以选择性地形成字线选择信号。 用于发送这些字线信号的主字线M0000至M0003与子字线SW000至SW255并联布置。 子字线驱动电路SWD000〜SWD255还通过组合至少2位的字线选择信号而耦合到各个子字线，以使相应的子字线选择性地选择成选定的状态。

公开(公告)号：US4951259A

公开(公告)日：1990-08-21

申请号：US156742

申请日：1988-02-18

申请人： Yoichi Sato ,  Satoshi Shinagawa

发明人： Yoichi Sato ,  Satoshi Shinagawa

IPC分类号： G11C11/413 ,  G11C8/08

CPC分类号： G11C8/08

摘要： A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.

摘要翻译： 提供一种半导体存储器件，其包括耦合到字线驱动器的输入的多个字线驱动器和逻辑解码电路。 在大存储器阵列中，由于字线驱动器晶体管必须相对较大，所以字线驱动电路可以在逻辑解码电路的输出上放置大的电容性负载。 逻辑解码电路上的这种大负载不利地影响存储器的操作速度。 因此，为了减小该负载，在逻辑解码电路的输出和字线驱动器之间提供切换装置。 可以根据预解码器的控制输出信号来控制该切换装置，以将逻辑解码电路的输出分别连接到字线驱动器。 还可以提供复位MOSFET以防止字线驱动器的输入浮动。

公开(公告)号：US5317537A

公开(公告)日：1994-05-31

申请号：US888493

申请日：1992-05-27

申请人： Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

发明人： Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C8/16 ,  H04Q3/52 ,  H04Q11/04 ,  G11C13/00

CPC分类号： G11C7/14 ,  G11C8/16

摘要： A multi-port memory device has a memory cell array including one or more memory blocks each of which has a plurality of memory cells arranged in rows and columns, and a plurality of dummy cells, with one dummy cell being provided for each row of memory cells in each of the memory blocks so that the dummy cells are connected with associated ones of the word lines extending in the row direction. The dummy cells are further connected with dummy cell bit lines extending in the column direction. Sense amplifiers are connected to receive outputs of those memory cells in the memory cell array which are selected in a memory cell selection operation and outputs of those dummy cells among the plurality of dummy cells which are selected in the memory cell selection operation for amplifying differences between the selected memory cell outputs and the selected dummy cell outputs. Precharging and shielding arrangements are also provided for improved operation.

摘要翻译： 多端口存储器件具有包括一个或多个存储器块的存储单元阵列，每个存储块具有以行和列排列的多个存储器单元，以及多个虚设单元，每个存储器行提供一个虚拟单元 每个存储器块中的单元，使得虚设单元与在行方向上延伸的字线相关联地连接。 虚拟单元进一步与在列方向上延伸的虚拟单元位线连接。 连接感测放大器以接收在存储单元选择操作中选择的存储单元阵列中的这些存储单元的输出，并且在存储单元选择操作中选择的多个虚设单元中的这些虚设单元的输出， 所选择的存储单元输出和所选择的虚拟单元输出。 还提供了预充电和屏蔽装置，以改善操作。