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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20090101969A1

    公开(公告)日：2009-04-23

    申请号：US12248577

    申请日：2008-10-09

    申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

    发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.

    摘要翻译： 一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动 响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100207190A1

    公开(公告)日：2010-08-19

    申请号：US12705231

    申请日：2010-02-12

    申请人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

    发明人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

    摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿层叠体的堆叠方向排列，半导体柱沿着第一方向排列成矩阵构造，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透相互不同的控制栅电极。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20130109157A1

    公开(公告)日：2013-05-02

    申请号：US13723601

    申请日：2012-12-21

    申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

    发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

    摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

    摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20120135593A1

    公开(公告)日：2012-05-31

    申请号：US13366509

    申请日：2012-02-06

    申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

    发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

    摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100072538A1

    公开(公告)日：2010-03-25

    申请号：US12534576

    申请日：2009-08-03

    申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

    发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hideaki AOCHI

    IPC分类号： H01L27/115 ,  H01L21/8246

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

    摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。