公开(公告)号：US20060170078A1

公开(公告)日：2006-08-03

申请号：US11339564

申请日：2006-01-26

申请人： Masataka Moriya ,  Kazuhiko Kashima ,  Shinichi Miyano

发明人： Masataka Moriya ,  Kazuhiko Kashima ,  Shinichi Miyano

IPC分类号： H01L29/36

CPC分类号： H01L21/3225

摘要： There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 Ω·cm or more and 100 Ω·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 Ω·cm or more and 100 Ω·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less.

摘要翻译： 提供了可以防止部件本身的电阻率在半导体制造工艺中变化的硅部件，特别是在等离子体处理工艺中，从而使晶片加工均匀并且不会成为待加工晶片的杂质污染源 及其制造方法。 制造具有0.1Ω·cm以上且100Ω·cm以下的电阻率的硅构件，其步骤是制造掺杂有13个原子的元素周期表的P型硅单晶，其具有1Ω cm以上且100Ω·cm以下，并且通过在300℃以上且500℃以下的退火形成的氧供体将所述P型硅单晶变更为N型硅单晶。 或更少。

公开(公告)号：US20080277768A1

公开(公告)日：2008-11-13

申请号：US12172534

申请日：2008-07-14

申请人： Masataka MORIYA ,  Kazuhiko Kashima ,  Shinichi Miyano

发明人： Masataka MORIYA ,  Kazuhiko Kashima ,  Shinichi Miyano

IPC分类号： H01L27/00

CPC分类号： H01L21/3225

摘要： There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 Ω·cm or more and 100 Ω·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 Ω·cm or more and 100 Ω·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less.

摘要翻译： 提供了可以防止部件本身的电阻率在半导体制造工艺中变化的硅部件，特别是在等离子体处理工艺中，从而使晶片加工均匀并且不会成为待加工晶片的杂质污染源 及其制造方法。 制造具有0.1Ω·cm以上且100Ω·cm以下的电阻率的硅构件，其步骤是制造掺杂有13个原子的元素周期表的P型硅单晶，其具有1Ω cm以上且100Ω·cm以下，并且通过在300℃以上且500℃以下的退火形成的氧供体将所述P型硅单晶变更为N型硅单晶。 或更少。

公开(公告)号：US07591209B2

公开(公告)日：2009-09-22

申请号：US10580553

申请日：2004-11-26

申请人： Daisuke Murakami ,  Masanobu Ueda ,  Kazuhiko Kashima ,  Junya Okida ,  Norihide Kimura

发明人： Daisuke Murakami ,  Masanobu Ueda ,  Kazuhiko Kashima ,  Junya Okida ,  Norihide Kimura

IPC分类号： B23B27/00 ,  B23B29/02

CPC分类号： B23B27/002 ,  B23B29/022 ,  Y10T82/2585 ,  Y10T408/76

摘要： An object is to provide a vibration suppressing cutting tool which is inexpensive and can damp chattering extremely effectively, and which is simple in structure and is applicable to a wide variety of machining diameters and cutting conditions.The shank 2 of the holder 1 is formed with a pocket 4. In the pocket 4, a vibration suppressing piece 5 is received so as to be movable relative to the holder 1 and not protrudable from the pocket 4. Under kinetic energy from the holder during cutting, the vibration suppressing piece 5 alternately knocks against a pair of opposed inner wall surfaces 4a and 4b of the pocket along its surface, along a plurality of lines or on a plurality of points when the holder vibrates during cutting, thereby damping vibrations of the holder.

摘要翻译： 本发明的目的是提供一种廉价的振动抑制切削工具，并且可以非常有效地抑制振动，并且结构简单并且适用于各种加工直径和切割条件。 保持器1的柄部2形成有袋4.在口袋4中，振动抑制片5被容纳成相对于保持器1可移动并且不能从口袋4突出。在来自保持器的动能 在切割期间，当切割期间保持器振动时，振动抑制片5沿着其表面沿着多条线或多个点交替地撞击袋的一对相对的内壁表面4a和4b，由此阻尼 持有人

公开(公告)号：US20070068447A1

公开(公告)日：2007-03-29

申请号：US11526868

申请日：2006-09-26

申请人： Koji Izunome ,  Yumiko Hirano ,  Takashi Watanabe ,  Kazuhiko Kashima ,  Hiroyuki Saito ,  Takeshi Senda

发明人： Koji Izunome ,  Yumiko Hirano ,  Takashi Watanabe ,  Kazuhiko Kashima ,  Hiroyuki Saito ,  Takeshi Senda

IPC分类号： C30B15/00 ,  C30B21/06 ,  C30B27/02 ,  C30B28/10 ,  C30B30/04

CPC分类号： C30B15/203 ,  C30B15/04 ,  C30B29/06

摘要： In order to control a crystal defective area, to inhibit slip generation at the time of annealing treatment, and to manufacture a high quality silicon wafer of high strength with sufficient yields, a method of manufacturing a silicon wafer is provided in which a silicon single crystal is grown by way of Czochralski method under conditions where an oxygen concentration is 0.9×1018 atoms/cm3 or more and an oxidization induced stacking fault density is the maximum in an area within 20 mm of a wafer circumference, and an as-grown defect density of the wafer obtained by slicing the silicon single crystal is 1×107/cm3 or more over the whole region of the wafer.

摘要翻译： 为了控制晶体缺陷区域，为了抑制退火处理时的滑移产生，以及以高产率制造高强度的高质量硅晶片，提供了一种制造硅晶片的方法，其中硅单晶 在氧浓度为0.9×10 18原子/ cm 3以上的条件下通过切克劳斯基法生长，并且氧化诱导的堆垛层错密度在区域中是最大的 在晶片圆周的20mm以内，通过对硅单晶进行切片而获得的晶片的生长缺陷密度为1×10 7 / cm 3以上 晶片的区域。

公开(公告)号：US08476149B2

公开(公告)日：2013-07-02

申请号：US12512492

申请日：2009-07-30

申请人： Hiromichi Isogai ,  Takeshi Senda ,  Eiji Toyoda ,  Kumiko Murayama ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Yoichiro Mochizuki ,  Akihiko Kobayashi ,  Senlin Fu

发明人： Hiromichi Isogai ,  Takeshi Senda ,  Eiji Toyoda ,  Kumiko Murayama ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Yoichiro Mochizuki ,  Akihiko Kobayashi ,  Senlin Fu

IPC分类号： H01L29/36

CPC分类号： H01L21/324 ,  C30B29/06 ,  C30B33/02 ,  H01L21/3225

摘要： A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

摘要翻译： 将通过切克劳斯基法生长的硅单晶锭制成的硅晶片在氧化气体气氛中在1300℃以上但小于1380℃的最高温度（T1）下进行快速加热/冷却热处理 氧分压为20％以上但小于100％。 根据本发明的硅晶片在至少包括硅晶片的器件有源区的无缺陷区（DZ层）中具有0.7×10 18原子/ cm 3的氧固溶体浓度的高氧浓度区域 以上，同时无缺陷区域含有过饱和状态的间隙硅。

公开(公告)号：US20100197146A1

公开(公告)日：2010-08-05

申请号：US12656232

申请日：2010-01-21

申请人： Takeshi Senda ,  Hiromichi Isogai ,  Eiji Toyoda ,  Kumiko Murayama ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima

发明人： Takeshi Senda ,  Hiromichi Isogai ,  Eiji Toyoda ,  Kumiko Murayama ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima

IPC分类号： H01L21/302

CPC分类号： C30B33/02 ,  C30B29/06 ,  C30B33/005 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/67109

摘要： In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

摘要翻译： 在通过切片由切克劳斯基法制造的硅单晶锭进行切片而得到的晶片的热处理方法中，通过将保持时间设定为1200℃以上的最终温度，进行快速加热/冷却热处理， 在含有氧分压为1.0％以上且20％以下的氧和氩气的混合气体气氛中，硅的熔点以下等于或大于1秒且等于或小于60秒， 因此在硅晶片的表面上形成厚度为9.1nm以下或24.3nm以上的氧化膜。

公开(公告)号：US07193294B2

公开(公告)日：2007-03-20

申请号：US11002995

申请日：2004-12-03

申请人： Reiko Yoshimura ,  Tsukasa Tada ,  Koji Izunome ,  Kazuhiko Kashima

发明人： Reiko Yoshimura ,  Tsukasa Tada ,  Koji Izunome ,  Kazuhiko Kashima

IPC分类号： H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288

CPC分类号： H01L21/3225 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/76254 ,  H01L21/76259 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.

摘要翻译： 半导体衬底包括支撑衬底1，其具有用于吸杂杂质金属的吸杂位置10，设置在支撑衬底1上并包含单氧能量高于硅的元素的氧化物的嵌入绝缘膜2，以及 设置在嵌入绝缘膜2上的半导体层（SOI层）3。

公开(公告)号：US20060118868A1

公开(公告)日：2006-06-08

申请号：US11002995

申请日：2004-12-03

申请人： Reiko Yoshimura ,  Tsukasa Tada ,  Koji Izunome ,  Kazuhiko Kashima

发明人： Reiko Yoshimura ,  Tsukasa Tada ,  Koji Izunome ,  Kazuhiko Kashima

IPC分类号： H01L27/12 ,  H01L29/06

CPC分类号： H01L21/3225 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/76254 ,  H01L21/76259 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.

摘要翻译： 半导体衬底包括支撑衬底1，其具有用于吸杂杂质金属的吸杂位置10，设置在支撑衬底1上并包含单氧能量高于硅的元素的氧化物的嵌入绝缘膜2，以及 设置在嵌入绝缘膜2上的半导体层（SOI层）3。

公开(公告)号：US4910156A

公开(公告)日：1990-03-20

申请号：US136851

申请日：1987-12-22

申请人： Shin'ichiro Takasu ,  Michihiro Ohwa ,  Kazuhiko Kashima ,  Eiichi Toji ,  Kazumoto Homma

发明人： Shin'ichiro Takasu ,  Michihiro Ohwa ,  Kazuhiko Kashima ,  Eiichi Toji ,  Kazumoto Homma

IPC分类号： C30B31/20 ,  H01L21/261 ,  H01L21/00 ,  H01L21/02 ,  H01L21/26 ,  H01L21/263

CPC分类号： H01L21/263 ,  C30B31/20 ,  H01L21/261 ,  Y10S148/165

摘要： A silicon wafer and a method of producing a silicon wafer comprising a phosphor-doping method of doping phosphor into a single silicon crystals by transmuting isotope Si.sup.30 contained in said single silicon crystals made by the CZ method or the MCZ method into p.sup.31 under neutron irradiation to said single silicon crystals.

摘要翻译： 一种硅晶片和一种硅晶片的制造方法，其特征在于，在中子照射下，通过将由CZ法或MCZ法制成的所述单晶硅中所含的同位素Si30转化为p31，将掺杂荧光体的磷掺杂方法掺杂到单晶硅晶体中， 所述单晶硅晶体。

公开(公告)号：US20120139088A1

公开(公告)日：2012-06-07

申请号：US13322080

申请日：2010-05-28

申请人： Takeshi Senda ,  Hiromichi Isogai ,  Eiji Toyoda ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima ,  Hiroyuki Saito

发明人： Takeshi Senda ,  Hiromichi Isogai ,  Eiji Toyoda ,  Koji Araki ,  Tatsuhiko Aoki ,  Haruo Sudo ,  Koji Izunome ,  Susumu Maeda ,  Kazuhiko Kashima ,  Hiroyuki Saito

IPC分类号： H01L29/02 ,  H01L21/26

CPC分类号： H01L21/3225 ,  Y10S438/928

摘要： A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

摘要翻译： 提供了一种用于防止大块区域中的空隙缺陷成为装置处理中的污染源和滑移产生的硅晶片。 并且提供了一种用于在晶片表面附近的区域中减少诸如COP之类的晶体缺陷的热处理方法作为器件有源区。 硅晶片具有作为无缺陷区域的表面区域1和包括多面体的空隙的主体区域2，其基本形状为八面体，多面体的角部为弯曲形状，内壁 氧化膜去除空隙缺陷。 通过进行热处理方法来提供硅晶片，当将通过CZ方法制造的硅晶片经受RTP时，将待供给的气体，空间的内部压力和最大可实现温度设定为预定值。