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    Method of manufacturing a semiconductor device
    1.
    发明授权
    Method of manufacturing a semiconductor device 有权

    公开(公告)号：US06825492B2

    公开(公告)日：2004-11-30

    申请号：US10775128

    申请日：2004-02-11

    申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    IPC分类号： H01H2904

    CPC分类号： G06Q30/02 ,  G06Q30/0256 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/14678 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/3244

    摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

    Method of manufacturing a semiconductor device
    2.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07351605B2

    公开(公告)日：2008-04-01

    申请号：US10994390

    申请日：2004-11-23

    申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/14625 ,  H01L27/14665 ,  H01L27/14678 ,  H01L27/14692 ,  H01L29/78621 ,  H01L31/125

    摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

    摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。

    Method of manufacturing a semiconductor device
    3.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050093037A1

    公开(公告)日：2005-05-05

    申请号：US10994390

    申请日：2004-11-23

    申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    IPC分类号： H01L21/77 ,  H01L27/12 ,  H01L27/146 ,  H01L29/786 ,  H01L31/062 ,  H01L31/12

    CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/14625 ,  H01L27/14665 ,  H01L27/14678 ,  H01L27/14692 ,  H01L29/78621 ,  H01L31/125

    摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

    摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。

    Method of manufacturing a semiconductor device
    4.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06692984B2

    公开(公告)日：2004-02-17

    申请号：US10117345

    申请日：2002-04-08

    申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

    IPC分类号： H01L2100

    CPC分类号： H01L27/14609 ,  H01L27/14692 ,  H01L27/15

    摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

    摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。