公开(公告)号：US06825492B2

公开(公告)日：2004-11-30

申请号：US10775128

申请日：2004-02-11

申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

IPC分类号： H01H2904

CPC分类号： G06Q30/02 ,  G06Q30/0256 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/14678 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/3244

摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

公开(公告)号：US07351605B2

公开(公告)日：2008-04-01

申请号：US10994390

申请日：2004-11-23

申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/14625 ,  H01L27/14665 ,  H01L27/14678 ,  H01L27/14692 ,  H01L29/78621 ,  H01L31/125

摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。

公开(公告)号：US20050093037A1

公开(公告)日：2005-05-05

申请号：US10994390

申请日：2004-11-23

申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

IPC分类号： H01L21/77 ,  H01L27/12 ,  H01L27/146 ,  H01L29/786 ,  H01L31/062 ,  H01L31/12

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/14625 ,  H01L27/14665 ,  H01L27/14678 ,  H01L27/14692 ,  H01L29/78621 ,  H01L31/125

摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。

公开(公告)号：US06692984B2

公开(公告)日：2004-02-17

申请号：US10117345

申请日：2002-04-08

申请人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

发明人： Masato Yonezawa ,  Hajime Kimura ,  Yu Yamazaki ,  Jun Koyama ,  Yasuko Watanabe

IPC分类号： H01L2100

CPC分类号： H01L27/14609 ,  H01L27/14692 ,  H01L27/15

摘要： The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

摘要翻译： 在制造在绝缘表面上具有晶体管和光电转换元件的半导体器件的方法中，掩模的数量减少。 在本发明的制造方法中，同时形成用作晶体管的源极区，漏极区和沟道形成区的半导体层，同时形成光电转换元件的n型半导体层和p型半导体层 形成。 与晶体管的源极配线和漏极布线同时形成与电子转换元件的n型半导体层和p型半导体层电连接的连接配线。 在使用提供一种导电类型的杂质元素的掺杂步骤中，n沟道晶体管的半导体层和光电转换元件的n型半导体层同时掺杂有杂质元素和p沟道的半导体层 晶体管和光电转换元件的p型半导体层同时掺杂有杂质元素。

公开(公告)号：US08253446B2

公开(公告)日：2012-08-28

申请号：US13369637

申请日：2012-02-09

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： H03B1/00

CPC分类号： H03F3/45179 ,  G11C27/028 ,  H03F3/082 ,  H03F3/45183 ,  H03K19/00384

摘要： The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

摘要翻译： 晶体管受到阈值电压或迁移率的影响，这是由于由于制造工艺或使用的衬底的差异以及沟道区域晶体状态的变化导致的栅极绝缘膜的变化的因素的集合。 本发明提供了一种电路，其电路具有电容元件的两个电极可以保持特定晶体管的栅极 - 源极电压。 本发明提供一种具有能够通过使用恒流源在电容元件的两个电极之间设置电位差的功能的电路。

公开(公告)号：US20060044044A1

公开(公告)日：2006-03-02

申请号：US11197427

申请日：2005-08-05

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： H03K17/687

CPC分类号： G09G3/3225 ,  G09G3/3648 ,  G09G2300/0833 ,  G09G2300/0876 ,  H01L27/0629 ,  H03F3/45 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2203/45112 ,  H03F2203/45628 ,  H03K19/00384 ,  H03K19/01728

摘要： A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

公开(公告)号：US08149043B2

公开(公告)日：2012-04-03

申请号：US12722786

申请日：2010-03-12

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： H03K17/687

CPC分类号： H03F3/45179 ,  G11C27/028 ,  H03F3/082 ,  H03F3/45183 ,  H03K19/00384

摘要： The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

公开(公告)号：US07456625B2

公开(公告)日：2008-11-25

申请号：US11559435

申请日：2006-11-14

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： G05F5/00 ,  G05F1/40 ,  G05F1/44

CPC分类号： H03K17/6871 ,  H02M7/538 ,  H02P8/00 ,  H03K17/145 ,  H04L25/0264

摘要： As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a threshold voltage and mobility of a transistor.This invention provides an electric circuit which used a rectification type device in which an electric current is generated only in a single direction, when an electric potential difference was applied to electrodes at both ends of the device. Then, the invention provides an electric circuit which utilized a fact that, when a signal voltage is inputted to one terminal of the rectification type device, an electric potential of the other terminal becomes an electric potential offset only by the threshold voltage of the rectification type device.

摘要翻译： 对于晶体管，重叠是由于制造工艺和所使用的衬底的差异导致的栅极绝缘膜的变化以及沟道形成区域中的结晶状态的变化的因素，因此发生变化 的晶体管的阈值电压和迁移率。 本发明提供了一种电路，当对器件的两端的电极施加电位差时，使用其中仅在单个方向上产生电流的整流型器件。 然后，本发明提供一种电路，其采用如下事实：当信号电压输入到整流型装置的一个端子时，另一个端子的电位仅由整流型的阈值电压变为电位偏移 设备。

公开(公告)号：US07348825B2

公开(公告)日：2008-03-25

申请号：US11197427

申请日：2005-08-05

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： H03K17/687

CPC分类号： G09G3/3225 ,  G09G3/3648 ,  G09G2300/0833 ,  G09G2300/0876 ,  H01L27/0629 ,  H03F3/45 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2203/45112 ,  H03F2203/45628 ,  H03K19/00384 ,  H03K19/01728

摘要： A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

摘要翻译： 晶体管由于由制造工艺或要使用的衬底的差异引起的栅极绝缘膜的变化等因素的积累导致的阈值电压或迁移率的变化以及沟道形成区域的晶体状态的变化 。 本发明提供一种电路，其布置成使得电容器件的两个电极可以在特定晶体管的栅极和源极之间保持电压。 此外，本发明提供一种电路，其具有能够将电容元件的两电极之间的电位差设定为特定晶体管的阈值电压的功能。

公开(公告)号：US08314601B2

公开(公告)日：2012-11-20

申请号：US13327942

申请日：2011-12-16

申请人： Hajime Kimura ,  Yasuko Watanabe

发明人： Hajime Kimura ,  Yasuko Watanabe

IPC分类号： G05F5/00 ,  G05F1/40 ,  G05F1/56

CPC分类号： H03K17/6871 ,  H02M7/538 ,  H02P8/00 ,  H03K17/145 ,  H04L25/0264

摘要： As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a threshold voltage and mobility of a transistor.This invention provides an electric circuit which used a rectification type device in which an electric current is generated only in a single direction, when an electric potential difference was applied to electrodes at both ends of the device. Then, the invention provides an electric circuit which utilized a fact that, when a signal voltage is inputted to one terminal of the rectification type device, an electric potential of the other terminal becomes an electric potential offset only by the threshold voltage of the rectification type device.

摘要翻译： 对于晶体管，重叠是由于制造工艺和所使用的衬底的差异导致的栅极绝缘膜的变化以及沟道形成区域中的结晶状态的变化的因素，因此发生变化 的晶体管的阈值电压和迁移率。 本发明提供了一种电路，当对器件的两端的电极施加电位差时，使用其中仅在单个方向上产生电流的整流型器件。 然后，本发明提供一种电路，其利用了如下事实：当信号电压输入到整流型装置的一个端子时，另一个端子的电位仅由整流型的阈值电压变为电位偏移 设备。