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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090166746A1

    公开(公告)日：2009-07-02

    申请号：US12342453

    申请日：2008-12-23

    申请人： Junichi Mitani ,  Satoshi Nakai ,  Kazushi Fujita

    发明人： Junichi Mitani ,  Satoshi Nakai ,  Kazushi Fujita

    IPC分类号： H01L21/762 ,  H01L27/088 ,  G06F17/50

    CPC分类号： H01L21/823456 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

    摘要翻译： 半导体器件具有设置在半导体衬底上的第一导电类型的第一和第二有源区，设置在半导体衬底上的第二导电类型的第三和第四有源区，第二和第四有源区的尺寸较大 分别设置为与第一有源区域相邻并且具有第一宽度的第一导电图案，与第二有源区域相邻设置并且具有大于第一宽度的第二宽度的第二导电图案 第三导电图案，其布置成与所述第三有源区相邻并且具有第三宽度; 以及第四导电图案，其布置成与所述第四有源区相邻并且具有小于所述第三宽度的第四宽度。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07075182B2

    公开(公告)日：2006-07-11

    申请号：US10968167

    申请日：2004-10-20

    申请人： Junichi Mitani ,  Yoshimori Asai

    发明人： Junichi Mitani ,  Yoshimori Asai

    IPC分类号： H01L23/48

    CPC分类号： H01L27/115 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device comprises a first conductive pattern 42, a second conductive pattern 42 formed adjacent to the first conductive pattern 42, a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42, a second conductor plug 62n formed over a prescribed region of the first conductive pattern 42, a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42, which is adjacent to a prescribed region of the first conductive pattern 42, a fourth conductor plug 62n+1 formed over a prescribed region of the second conductive pattern 42, a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62. The fourth conductor plug 62n+1 is arranged a position which is offset from the second conductor plug 62n. The conductor plugs 62n, 62n+1 are offset each other in the longitudinal direction of the interconnections, whereby the parts of the interconnections having an increased width can be distanced from each other. Thus, the interconnections can be arranged at a small pitch without using an ArF exposure system and a half tone phase shift mask, which are expensive. Accordingly, the semiconductor device of high integration is provided at low costs while ensuring high fabrication yields.

    摘要翻译： 半导体器件包括第一导电图案42，与第一导电图案42相邻形成的第二导电图案42，形成在第一导电图案42的规定区域下方的第一导体插塞28，第二导体插塞62 形成在第一导电图案42的规定区域上的第三导体插塞28，形成在第二导电图案42的与第一导电图案42的规定区域相邻的规定区域下方的第三导体插塞28， 形成在第二导电图案42的规定区域上的插头62＆lt; n + 1＆gt;形成在第一导电图案42上方并连接到第二导体插塞62a的第三导电图案64，以及第四导电图案 图案64形成在第二导电图案42上方并连接到第四导体插塞62。 第四导体插头62＆lt; n + 1＆gt;被布置在与第二导体插头62N偏移的位置。 导线插头62N，62N + 1 +在相互连接的纵向方向彼此相互偏移，由此具有增加的宽度的互连部分可以远离 彼此。 因此，可以以小的间距布置互连，而不使用昂贵的ArF曝光系统和半色调相移掩模。 因此，在确保高制造成品率的同时以低成本提供高集成度的半导体器件。

    Semiconductor device
    6.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050236713A1

    公开(公告)日：2005-10-27

    申请号：US10968167

    申请日：2004-10-20

    申请人： Junichi Mitani ,  Yoshimori Asai

    发明人： Junichi Mitani ,  Yoshimori Asai

    IPC分类号： H01L21/768 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8247 ,  H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device comprises a first conductive pattern 42, a second conductive pattern 42 formed adjacent to the first conductive pattern 42, a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42, a second conductor plug 62n formed over a prescribed region of the first conductive pattern 42, a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42, which is adjacent to a prescribed region of the first conductive pattern 42, a fourth conductor plug 62n+1formed over a prescribed region of the second conductive pattern 42, a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62. The fourth conductor plug 62n+1 is arranged a position which is offset from the second conductor plug 62n. The conductor plugs 62n, 62n+1 are offset each other in the longitudinal direction of the interconnections, whereby the parts of the interconnections having an increased width can be distanced from each other. Thus, the interconnections can be arranged at a small pitch without using an ArF exposure system and a half tone phase shift mask, which are expensive. Accordingly, the semiconductor device of high integration is provided at low costs while ensuring high fabrication yields.

    摘要翻译： 半导体器件包括第一导电图案42，与第一导电图案42相邻形成的第二导电图案42，形成在第一导电图案42的规定区域下方的第一导体插塞28，第二导体插塞62 形成在第一导电图案42的规定区域上的第三导体插塞28，形成在第二导电图案42的与第一导电图案42的规定区域相邻的规定区域下方的第三导体插塞28， 形成在第二导电图案42的规定区域上的插头62＆lt; n + 1＆gt;形成在第一导电图案42上方并连接到第二导体插塞62a的第三导电图案64，以及第四导电图案 图案64形成在第二导电图案42上方并连接到第四导体插塞62。 第四导体插头62＆lt; n + 1＆gt;被布置在与第二导体插头62N偏移的位置。 导线插头62N，62N + 1 +在相互连接的纵向方向彼此相互偏移，由此具有增加的宽度的互连部分可以远离 彼此。 因此，可以以小的间距布置互连，而不使用昂贵的ArF曝光系统和半色调相移掩模。 因此，在确保高制造成品率的同时以低成本提供高集成度的半导体器件。

    Semiconductor device having triple well structure
    7.
    发明授权
    Semiconductor device having triple well structure 有权
    具有三重阱结构的半导体器件

    公开(公告)号：US06727573B2

    公开(公告)日：2004-04-27

    申请号：US09826364

    申请日：2001-04-05

    申请人： Junichi Mitani ,  Makoto Yasuda

    发明人： Junichi Mitani ,  Makoto Yasuda

    IPC分类号： H01L2900

    CPC分类号： H01L21/76213 ,  H01L21/823892

    摘要： The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42. This constitution of the semiconductor device permits the diffused layer 42 and the well 28 to be formed by the use of one and the same mask, whereby in electrically isolating the well 44 from the semiconductor substrate by the well 28 and the diffused layer 42, the triple well can be formed without increasing lithography steps.

    摘要翻译： 根据本发明的半导体器件包括：第一导电类型的半导体衬底10; 形成在围绕半导体衬底10的区域20的区域18中形成的不同于第一导电类型的第二导电类型的阱28; 形成第二导电类型的扩散层42，埋在半导体衬底10中的区域20中并在其一侧连接到阱28; 以及第一导电类型的阱44，其形成在半导体衬底10中，在其表面侧的区域20中，由阱28和扩散层42与半导体衬底10的静止区域电隔离。这种构造 的半导体器件允许通过使用相同的掩模形成扩散层42和阱28，由此通过阱28和扩散层42将阱44与半导体衬底电隔离，三阱 可以在不增加光刻步骤的情况下形成。

    Semiconductor device and method for fabricating the same
    8.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06335552B1

    公开(公告)日：2002-01-01

    申请号：US08928770

    申请日：1997-09-12

    申请人： Junichi Mitani

    发明人： Junichi Mitani

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L27/10873

    摘要： The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

    摘要翻译： 半导体器件包括：MOSFET，其包括形成在形成于半导体衬底上的栅极的两侧上的一对杂质扩散区域; 绝缘膜，覆盖所述MOSFET的顶部并且具有在形成的所述杂质扩散区域之一上开口的通孔; 以及电容器，其形成在所述通孔的内部的至少一部分中，所述通孔在其表面之间具有比在其表面处更大的直径或在其表面和底部之间的中间部分处具有比所述通孔 表面及其底部。

    Semiconductor device and method of manufacturing the same
    10.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07009234B2

    公开(公告)日：2006-03-07

    申请号：US10268677

    申请日：2002-10-11

    申请人： Junichi Mitani

    发明人： Junichi Mitani

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H01L21/76802 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76834 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

    摘要翻译： 半导体器件的制造方法包括以下步骤：形成覆盖第一区域（2）和第一级导电插塞（15b）中的布线（16）的至少侧表面的蚀刻停止绝缘膜（18） 在第二区域（3）中，然后在蚀刻停止绝缘膜（18）和布线（16）上形成绝缘膜（20,28），然后在第一级导电插塞（15b）上形成孔（28） ）通过蚀刻绝缘膜（20,28）的一部分直到蚀刻停止绝缘膜（18）暴露，然后通过选择性地蚀刻蚀刻停止绝缘膜来暴露第一级导电插塞（15b）的上表面 （18）穿过所述孔（28），然后在所述孔（28）中形成第二级导电塞（31a）。