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1.发明授权公开(公告)号：US08392761B2
公开(公告)日：2013-03-05
申请号：US12751005
申请日：2010-03-31
IPC分类号： G06F11/00
CPC分类号： G06F11/1402 , G06F11/1438 , G06F11/1658 , G06F11/2025 , G06F11/2035 , G06F11/2097
摘要： A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.
摘要翻译： 示出了包括可操作地连接到存储器的处理器的系统和方法，所述处理器包括存储器控制器以控制对存储器的访问。 该系统和方法还包括服务处理器，共同位于公共板上并且可操作地连接到处理器和存储器，服务处理器包括附加存储器控制器以控制对作为检查点状态的一部分的对存储器的访问。
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2.发明申请公开(公告)号：US20110246828A1
公开(公告)日：2011-10-06
申请号：US12751005
申请日：2010-03-31
CPC分类号： G06F11/1402 , G06F11/1438 , G06F11/1658 , G06F11/2025 , G06F11/2035 , G06F11/2097
摘要： A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.
摘要翻译： 示出了包括可操作地连接到存储器的处理器的系统和方法，所述处理器包括存储器控制器以控制对存储器的访问。 该系统和方法还包括服务处理器，共同位于公共板上并且可操作地连接到处理器和存储器，服务处理器包括附加存储器控制器以控制对作为检查点状态的一部分的对存储器的访问。
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公开(公告)号：US09608922B2
公开(公告)日：2017-03-28
申请号：US13993575
申请日：2011-12-23
申请人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
发明人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
IPC分类号： H04L12/24 , H04L12/825 , G06F15/78
CPC分类号： H04L47/25 , G06F15/7825 , H04L47/263 , Y02D10/12 , Y02D10/13 , Y02D50/10
摘要： An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.
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公开(公告)号：US20140019823A1
公开(公告)日：2014-01-16
申请号：US13992504
申请日：2011-12-22
IPC分类号： H03M13/29
CPC分类号： H03M13/2906 , G06F1/3275 , G06F1/3296 , G06F11/1064 , G06F12/0895 , H03M13/09 , H03M13/356 , Y02D10/14 , Y02D10/172
摘要： Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.
摘要翻译： 描述了用于降低数据高速缓存功耗和错误保护开销的系统，设备和方法的实施例。 在一些实施例中，数据高速缓存被分割成高速缓存部分。 每个缓存部分存储具有不同容错的数据，并且使用与其它高速缓存部分不同的错误检测机制。
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公开(公告)号：US09405647B2
公开(公告)日：2016-08-02
申请号：US13994697
申请日：2011-12-30
IPC分类号： G06F11/00 , G06F11/263 , G06F9/45
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译： 至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。 对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由 二进制翻译器
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公开(公告)号：US20130318401A1
公开(公告)日：2013-11-28
申请号：US13994697
申请日：2011-12-30
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译： 至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。 对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由 二进制翻译器
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公开(公告)号：US20100194470A1
公开(公告)日：2010-08-05
申请号：US12366234
申请日：2009-02-05
申请人： Matteo Monchiero , Jacob B. Leverich , Parthasarathy Ranganathan , Norman Paul Jouppi , Vanish Talwar
发明人： Matteo Monchiero , Jacob B. Leverich , Parthasarathy Ranganathan , Norman Paul Jouppi , Vanish Talwar
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L23/36 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H03K19/0016 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.
摘要翻译： 集成电路封装包括设置在基板上的数字逻辑管芯; 以及在基板上与数字逻辑管芯垂直堆叠的插入器管芯。 插入器管芯包括至少一个垂直晶体管，其构造成选择性地向数字逻辑管芯的一部分提供电功率。
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公开(公告)号：US09262306B2
公开(公告)日：2016-02-16
申请号：US12695145
申请日：2010-01-27
CPC分类号： G06F11/3672 , G06F21/53 , G06F2221/2149
摘要： An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices.
摘要翻译： 建立了分发软件应用程序的在线市场。 从在线市场，设备能够选择相应的软件应用程序，并开始测试所选择的软件应用程序与在相应的安全测试环境中操作的测试工具相结合，从而屏蔽设备免受测试所选择的软件应用程序引起的潜在的不利影响 。 测试工具生成与一个或多个标准相关的测试数据，用于验证所选择的软件应用程序。 对于所选择的一个或多个软件应用中的每一个，确定是否将软件应用程序分类为经认证的软件应用程序，其基于在由多个软件应用程序发起的软件应用程序的测试期间生成的测试数据的评估 设备。
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公开(公告)号：US09112537B2
公开(公告)日：2015-08-18
申请号：US13992504
申请日：2011-12-22
CPC分类号： H03M13/2906 , G06F1/3275 , G06F1/3296 , G06F11/1064 , G06F12/0895 , H03M13/09 , H03M13/356 , Y02D10/14 , Y02D10/172
摘要： Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.
摘要翻译： 描述了用于降低数据高速缓存功耗和错误保护开销的系统，设备和方法的实施例。 在一些实施例中，数据高速缓存被分割成高速缓存部分。 每个缓存部分存储具有不同容错的数据，并且使用与其它高速缓存部分不同的错误检测机制。
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10.发明申请TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOUT A CENTRALIZED MECHANISM 审中-公开在没有集中化机制的情况下跟踪片上多线程网络的分布式执行公开(公告)号：US20140237018A1
公开(公告)日：2014-08-21
申请号：US13993313
申请日：2011-12-23
IPC分类号： H04L12/24
CPC分类号： H04L41/046 , G06F15/7825
摘要： A method and system for tracking distributed execution on on-chip multinode networks, the method comprising: initiating, by a first node coupled to an on-chip network, execution of instructions on the first node for a distributed agent; initiating, by the first node, execution of instructions on a second node coupled to the on-chip network for the distributed agent; initiating, by the second node, execution of instructions on a third node coupled to the on-chip network for the distributed agent, wherein the second node does not notify the first node of the initiated execution on the third node; providing reoccurring notification by the second and third nodes to all nodes coupled to the on-chip network that they continue to execute instructions for the distributed agent; and determining, by the first node, that execution of instructions for the distributed agent is complete by detecting an absence of reoccurring notifications from nodes the network.
摘要翻译： 一种用于跟踪片上多节点网络上的分布式执行的方法和系统，所述方法包括：由耦合到片上网络的第一节点发起用于分布式代理的所述第一节点上的指令的执行; 由所述第一节点发起在耦合到所述分布式代理的片上网络的第二节点上执行指令; 由所述第二节点发起在所述分布式代理上耦合到所述片上网络的第三节点上的指令的执行，其中所述第二节点不在所述第三节点上通知所述第一节点所述发起的执行; 提供由第二和第三节点向连接到片上网络的所有节点重发的通知，他们继续执行分发代理的指令; 以及由所述第一节点通过检测不存在来自所述网络的节点的再发送的通知来确定所述分布式代理的指令的执行是否完成。
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