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    Apparatus and Method For Coupling Implanted Electrodes to Nervous Tissue
    3.
    发明申请
    Apparatus and Method For Coupling Implanted Electrodes to Nervous Tissue 审中-公开
    将植入电极耦合到神经组织的装置和方法

    公开(公告)号：US20080214920A1

    公开(公告)日：2008-09-04

    申请号：US11995846

    申请日：2006-07-11

    申请人： Matthias Merz ,  Youri Ponomarev ,  Remco Pijnenburg

    发明人： Matthias Merz ,  Youri Ponomarev ,  Remco Pijnenburg

    IPC分类号： A61B5/04

    CPC分类号： A61B5/04001 ,  A61B5/6805 ,  A61N1/0529 ,  A61N1/0531 ,  A61N1/0534 ,  A61N1/0543 ,  A61N1/0551 ,  B82Y15/00

    摘要： An apparatus and method for improving electrical contact between an implanted device (10) for recording or stimulating neuronal activity and surrounding tissue (12) (e.g., brain tissue, nerve fibers, etc.). In an exemplary embodiment, a nanometer sized topographic structure (36, 136) (e.g., a nanometer scale pillar) is processed for electrical connection with a corresponding electrode (30, 32) of the implanted device (10). The nanometer scale topographic structure (36, 136) bridges a gap (26) between the implanted device (10) and surrounding tissue (12), thus improving neuron-electrode coupling therebetween. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells (20) can be used for sensing and/or stimulation thereof.

    摘要翻译： 一种用于改善用于记录或刺激神经元活动的植入装置（10）与周围组织（12）（例如脑组织，神经纤维等）之间的电接触的装置和方法。 在示例性实施例中，处理纳米尺度的地形结构（例如纳米尺度柱）（例如纳米尺度的柱），以与植入装置（10）的对应电极（30,32）电连接。 纳米级地形结构（36,136）桥接植入装置（10）和周围组织（12）之间的间隙（26），从而改善其间的神经元 - 电极耦合。 本公开还可以扩展到任何应用，其中可将单个或多个单元（20）的电容耦合用于感测和/或刺激它们。

    Apparatus and Method For Electrostimulation /Sensing in Vivo
    4.
    发明申请
    Apparatus and Method For Electrostimulation /Sensing in Vivo 审中-公开
    体内电刺激/感觉的装置和方法

    公开(公告)号：US20080200967A1

    公开(公告)日：2008-08-21

    申请号：US12066690

    申请日：2006-09-13

    申请人： Youri Ponomarev ,  Matthias Merz ,  Remco Pijnenburg

    发明人： Youri Ponomarev ,  Matthias Merz ,  Remco Pijnenburg

    IPC分类号： A61N1/04

    CPC分类号： A61N1/0551 ,  A61N1/40

    摘要： An apparatus and method for electrostimulation treatment of neurological diseases is disclosed herein. The apparatus and method include an array (22) of sub-micron (and sub-cell size) FET electrodes (24) that are capacitively coupled to nervous system elements (both neurons (50) and axons (66)) as a replacement for traditional metal shanks in both single- and multi-electrode(s) electrostimulation implantable devices. By using such an approach, significant improvements in selectivity, power consumption and biocompatibility can be achieved, as well as relying on mainstream IC manufacture techniques for the manufacture thereof, making it cost-effective. The present disclosure can also be extended to any application where capacitive coupling to single or multiple cells can be used for sensing and/or stimulation thereof.

    摘要翻译： 本文公开了神经疾病的电刺激治疗的装置和方法。 该装置和方法包括电容耦合到神经系统元件（神经元（50）和轴突（66））的亚微米（和子电池尺寸）FET电极（24）的阵列（22） 单电极和多电极电刺激可植入装置中的传统金属柄。 通过使用这种方法，可以实现选择性，功率消耗和生物相容性的显着改善，以及依靠主流IC制造技术来制造它，使其具有成本效益。 本公开还可以扩展到任何可以将单个或多个单元的电容耦合用于感测和/或刺激的应用。

    BRANCHING THERAPY ELEMENTS AND METHOD OF THEIR INSERTION INTO LIVING TISSUE
    5.
    发明申请
    BRANCHING THERAPY ELEMENTS AND METHOD OF THEIR INSERTION INTO LIVING TISSUE 审中-公开
    分配治疗单元及其入侵组织的方法

    公开(公告)号：US20100010550A1

    公开(公告)日：2010-01-14

    申请号：US12442528

    申请日：2007-09-20

    申请人： Youri Ponomarev ,  Matthias Merz ,  Remco Henricus Wilhelmus Pijnenburg

    发明人： Youri Ponomarev ,  Matthias Merz ,  Remco Henricus Wilhelmus Pijnenburg

    IPC分类号： A61N1/05 ,  A61M31/00 ,  A61B19/00

    CPC分类号： A61N1/0529 ,  A61N1/0534

    摘要： An implantable medical system for electrical recording and or providing therapy to a plurality of tissue sites without damage to surrounding blood vessels is disclosed comprising: an implant body having a plurality of therapy elements, the elements being hingedly attached at one end to the surface of the body and releasably extendable outward from the surface of the body at the other end; a release mechanism for each of the elements; and a coating material covering the body and the elements; wherein upon dissolution of the coating material after implantation, the release mechanism is capable of causing the elements to extend outward at one end from the surface of the body and into a plurality of tissue sites without damage to the surrounding blood vessels. The method of implanting the system into a body is also disclosed.

    摘要翻译： 公开了一种用于对多个组织部位进行电记录和/或对周围血管的损伤提供治疗的可植入医疗系统，包括：具有多个治疗元件的植入体，所述元件在一端铰接附接到 并且在另一端从主体的表面可释放地向外延伸; 用于每个元件的释放机构; 以及覆盖所述主体和所述元件的涂层材料; 其中，在植入后溶解涂层材料时，释放机构能够使元件在一端从身体的表面向外延伸并且进入多个组织部位而不损坏周围的血管。 还公开了将系统植入体内的方法。

    Method for forming a strained Si-channel in a MOSFET structure
    7.
    发明授权
    Method for forming a strained Si-channel in a MOSFET structure 有权
    在MOSFET结构中形成应变Si沟道的方法

    公开(公告)号：US07416957B2

    公开(公告)日：2008-08-26

    申请号：US10596422

    申请日：2004-11-30

    申请人： Youri Ponomarev

    发明人： Youri Ponomarev

    IPC分类号： H01L21/30

    CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02532

    摘要： Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer (3B) being adjacent to the buried silicon dioxide layer (BOX).

    摘要翻译： 在基板（1）上形成应变Si层的方法，包括在Si表面上形成外延SiGe层（4），以及通过在外延SiGe顶部外延生长Si层的应变Si层 层（4），由于外延生长，Si层被应变，其中衬底（1）是具有支撑层（1），掩埋二氧化硅层（BOX）和单晶Si（Si）的硅绝缘体衬底 表面层（3），所述方法还包括：Si表面层（3）和外延SiGe层（4）的离子注入，以将Si表面层（3）转变为非晶Si层（3B）和部分 的外延SiGe层（4）的非晶SiGe层（5）中的另一部分外延SiGe层（4）是剩余的单晶SiGe层（6），非晶Si层（3B），非晶SiGe 层和剩余的单晶SiGe层（6）在墓碑上形成层叠（3 B，5,6） 二氧化硅层（BOX），其中非晶Si层（3B）与掩埋二氧化硅层（BOX）相邻。

    Method for the Manufacture of a Semiconductor Device and a Semiconductor Device Obtained Through It
    8.
    发明申请
    Method for the Manufacture of a Semiconductor Device and a Semiconductor Device Obtained Through It 有权
    用于制造半导体器件的方法和通过它获得的半导体器件

    公开(公告)号：US20080093668A1

    公开(公告)日：2008-04-24

    申请号：US11722988

    申请日：2005-12-19

    申请人： Youri Ponomarev ,  Josine Loo

    发明人： Youri Ponomarev ,  Josine Loo

    IPC分类号： H01L29/786 ,  H01L21/84

    CPC分类号： H01L29/66772 ,  H01L29/78648

    摘要： The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode (7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed. Before the ion implantation (20), a mask (M1) is formed on both sides of the gate electrode (7) and at a distance thereof, whereby after the ion implantation (20) at the location of the mask (M1) also a change in property of the silicon is obtained. In this way the device (10) can be easily provided with lateral insulation regions. Also the end regions of the gate electrodes (7,8) can in this way be surrounded by insulation regions.

    摘要翻译： 本发明涉及具有半导体本体（2）的半导体器件（10），包括场效应晶体管，第一栅极电介质（6A）形成在沟道区域（5）的位置处的第一表面上， 它是第一栅电极（7），从半导体本体（2）的第一侧通过第一栅电极（7）的两侧执行沉没离子注入（20），该注入导致 与第一栅极电极（7）下方的硅的特性相比，在远离第一栅极电介质（6A）的沟道区域（5）的部分中与栅电极（7）的两侧的硅相比， 半导体主体（2）的第二表面通过选择性蚀刻在其中提供空腔（30），同时使用硅的性质变化。 第二栅极（6B，8）沉积在如此形成的空腔中。 在离子注入（20）之前，在栅电极（7）的两侧和其一定距离处形成掩模（M 1），由此在掩模（M1）的位置处的离子注入（20）之后， 也获得了硅的性质变化。 以这种方式，设备（10）可以容易地设置有侧向绝缘区域。 此外，栅电极（7,8）的端部区域也可以这样被绝缘区域包围。

    Method of manufacturing a semiconductor device having a pocket implant in channel region
    9.
    发明授权
    Method of manufacturing a semiconductor device having a pocket implant in channel region 有权
    制造在通道区域具有口袋植入物的半导体器件的方法

    公开(公告)号：US06544851B2

    公开(公告)日：2003-04-08

    申请号：US09784421

    申请日：2001-02-15

    申请人： Youri Ponomarev ,  Marian Nelia Webster ,  Charles Johan Joachim Dachs

    发明人： Youri Ponomarev ,  Marian Nelia Webster ,  Charles Johan Joachim Dachs

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/823842 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

    摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11,9) and a drain zone (12,9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). In this recess (16), a double-layer (20) is applied consisting of a second sub-layer (19) on top of a first sub-layer (18), which second sub-layer (19) is removed over part of its thickness until the first sub-layer is exposed, which first sub-layer (18) is selectively etched with respect to the second sub-layer (19) and the side walls (17) of the recess (16) to a depth, thereby forming trenches (21) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). Via these trenches (21) impurities of the first conductivity type are introduced into the semiconductor body (1), thereby forming pocket implants (22).

    摘要翻译： 在制造半导体器件的方法中，所述半导体器件包括第一导电类型的半导体本体（1），所述半导体本体（1）设置在具有与设置在所述表面处的沟道（13）绝缘的具有栅极（28）的晶体管的表面（2） 通过栅极电介质（26）将半导体本体（1）的结构（2）设置在包括具有凹部（16）的电介质层（14）的表面（2）上的结构，该凹部（16）与 源区（11,9）和设置在半导体本体（1）的表面（2）处的第二导电类型的漏区（12,9），并且具有基本上垂直于表面（2）延伸的侧壁 ）半导体本体（1）。 在该凹部（16）中，由在第一子层（18）的顶部上的第二子层（19）构成的双层（20），该第二子层（19）在部分 其厚度直到第一子层露出为止，将第一子层（18）相对于第二子层（19）和凹部（16）的侧壁（17）选择性地蚀刻到深度 从而形成基本上垂直于半导体本体（1）的表面（2）延伸的沟槽（21）。 通过这些沟槽（21）将第一导电类型的杂质引入半导体本体（1）中，从而形成袋状植入物（22）。

    Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure
    10.
    发明授权
    Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure 有权
    制造量子阱结构的半导体器件方法和包括这种量子阱结构的半导体器件

    公开(公告)号：US07951684B2

    公开(公告)日：2011-05-31

    申请号：US12429348

    申请日：2009-04-24

    申请人： Youri Ponomarev

    发明人： Youri Ponomarev

    IPC分类号： H01L21/76

    CPC分类号： H01L29/78696 ,  H01L29/1054 ,  H01L29/152 ,  H01L29/7782 ,  H01L29/7838 ,  H01L29/78687 ,  Y10S438/962

    摘要： A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6′), wherein the material of the insulating layers (6,6′) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths.In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.

    摘要翻译： 公开了一种用于在基板（2）上获得具有量子阱结构（4）的多层结构（3）的半导体器件（1）和方法。 量子阱结构（4）包括被绝缘层（6,6'）夹持的半导体层（5），其中绝缘层（6,6'）的材料优选具有高的介电常数。 在FET中，量子阱（4,9）用作通道，允许更高的驱动电流和更低的截止电流。 短信道效应降低。 多通道FET适用于甚至对于35nm以下的栅极长度。 在该方法中，通过高介电常数材料和半导体材料彼此交替地外延生长，优选地以MBE形成量子阱。