公开(公告)号：US5054834A

公开(公告)日：1991-10-08

申请号：US446196

申请日：1989-12-05

申请人： Mauro Alessandri ,  Renzo Carrera ,  Giulio Iannuzzi

发明人： Mauro Alessandri ,  Renzo Carrera ,  Giulio Iannuzzi

IPC分类号： H01L21/687

CPC分类号： H01L21/68707 ,  Y10S294/907

摘要： A gripper for the advantageously robotized handling of one or more silicon wafers (5) comprises a part (2, 102) which allows the gripper (1, 101) to be secured to an operating arm or other handling member (3), the part (2, 102) being rigid with a support structure (4, 104) for the silicon wafers. The structure (4, 104) comprises at least two mutually cooperating opposing jaws (9, 10; 109, 110) mobile relative to each other; the jaws (9, 10; 109, 110) are provided with at least one seat (16, 116) for adapting to the shape of the lateral edge (17) of the wafer (5) supported by the jaws during its handling. Advantageously, on one side (108) of the wafer support structure (104) there are provided at least two members (174) mobile relative to the side (108) and arranged to cooperate with a silicon wafer holder or boat, to enable this latter to be supported and handled.

摘要翻译： 用于有利地自动化处理一个或多个硅晶片（5）的夹持器包括允许夹持器（1,101）固定到操作臂或其他处理构件（3）的部分（2,102），所述部件 （2,102）与用于硅晶片的支撑结构（4,104）是刚性的。 结构（4,104）包括相对于彼此移动的至少两个相互配合的相对的钳口（9,10; 109,110）; 钳口（9,10; 109,110）设置有至少一个座（16,116），用于在其处理期间适应由钳口支撑的晶片（5）的侧边缘（17）的形状。 有利地，在晶片支撑结构（104）的一侧（108）上设置有至少两个可相对于侧面（108）移动的构件（174），并被布置成与硅晶片保持器或舟皿配合，以使后者 得到支持和处理。

公开(公告)号：US4703552A

公开(公告)日：1987-11-03

申请号：US689875

申请日：1985-01-09

申请人： Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

发明人： Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28

CPC分类号： H01L29/4933 ,  H01L21/823835 ,  Y10S148/082

摘要： The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

摘要翻译： 该方法提供在多晶硅的栅极层上形成金属硅化物层，并且对于CMOS对的每个晶体管，同时掺杂有源区和栅极多晶硅。 在通过该方法制造的结构中，栅电极是由金属硅化物覆盖的多晶硅，并且n沟道晶体管的栅电极掺杂有n型材料，而p沟道晶体管的栅电极掺杂 p型杂质。 这使得即使在非常高的集成密度的情况下也可以为两个晶体管产生低阈值电压。

公开(公告)号：US4176443A

公开(公告)日：1979-12-04

申请号：US957331

申请日：1978-11-03

申请人： Giulio Iannuzzi ,  Carlo C. deMartiis ,  Vittorio Del Bo ,  Luciano Gandolfi

发明人： Giulio Iannuzzi ,  Carlo C. deMartiis ,  Vittorio Del Bo ,  Luciano Gandolfi

IPC分类号： H01L21/60 ,  H01L23/532 ,  B01J17/00

CPC分类号： H01L24/05 ,  H01L23/53209 ,  H01L23/53223 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85801 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  Y10T29/49155

摘要： A silicon wafer, having a front surface with disjointed contact areas and a uniform rear surface, is provided at the contact areas of its front surface with respective pads each comprising a base layer of aluminum, a first intermediate layer of chromium or titanium, a second intermediate layer of nickel and an outer layer of gold or palladium. The rear surface is covered with a base layer of gold (or of a gold/arsenic alloy in the case of N-type silicon), a first intermediate layer of chromium, a second intermediate layer of nickel and an outer layer of gold or palladium to which a film of low-melting bonding agent (lead/tin solder) is applied. After testing and elimination of unsatisfactory wafer sections, the remaining sections are separated into dies placed on a conductive substrate; an extremity of a respective terminal lead, encased in a similar bonding agent, is then placed on the outer layer of each contact pad. All soldering operations are simultaneously performed in a furnace.

摘要翻译： 具有具有不连续接触区域和均匀后表面的前表面的硅晶片在其前表面的接触区域处设置有各自的焊盘，每个焊盘包括铝基底层，铬或钛的第一中间层，第二中间层 镍的中间层和金或钯的外层。 后表面覆盖有金（或在N型硅的情况下为金/砷合金）的基底层，铬的第一中间层，镍的第二中间层和金或钯的外层 使用低熔点粘合剂（铅/锡焊料）的薄膜。 在测试和消除不令人满意的晶片部分之后，将剩余的部分分离成放置在导电衬底上的管芯; 然后将封装在相似的粘合剂中的相应端子引线的末端放置在每个接触垫的外层上。 所有焊接操作都在炉子中同时进行。

公开(公告)号：US4718977A

公开(公告)日：1988-01-12

申请号：US773319

申请日：1985-09-06

申请人： Claudio Contiero ,  Giulio Iannuzzi ,  Giorgio De Santi ,  Fabrizio Andreani

发明人： Claudio Contiero ,  Giulio Iannuzzi ,  Giorgio De Santi ,  Fabrizio Andreani

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/532 ,  C23F1/02 ,  H01L29/44

CPC分类号： H01L23/53223 ,  H01L2924/0002

摘要： Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.

摘要翻译： 半导体器件或集成电路上不同厚度的金属化图案的结构和方法。 改进的结构和方法利用三层金属，以减少所需数量的加工步骤。 一个优选实施例需要单个金属沉积序列，随后是两个蚀刻步骤，而适用于较厚金属化的第二实施例仅需要两个沉积和两个蚀刻步骤。