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    Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content
    5.
    发明授权
    Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content 有权
    使用具有降低的碳含量的基于硅氧烷的氧化硅盖层的双重马氏体过程

    公开(公告)号：US07378343B2

    公开(公告)日：2008-05-27

    申请号：US11164285

    申请日：2005-11-17

    申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7681 ,  H01L21/76829

    摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

    摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

    DUAL DAMASCENE PROCESS UTILIZING TEOS-BASED SILICON OXIDE CAP LAYER HAVING REDUCED CARBON CONTENT
    6.
    发明申请
    DUAL DAMASCENE PROCESS UTILIZING TEOS-BASED SILICON OXIDE CAP LAYER HAVING REDUCED CARBON CONTENT 有权
    使用具有减少碳含量的基于TEOS的氧化硅膜层的双重增塑工艺

    公开(公告)号：US20070111514A1

    公开(公告)日：2007-05-17

    申请号：US11164285

    申请日：2005-11-17

    申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

    IPC分类号： H01L21/473

    CPC分类号： H01L21/7681 ,  H01L21/76829

    摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

    摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

    POROUS LOW-K DIELECTRIC FILM AND FABRICATION METHOD THEREOF
    7.
    发明申请
    POROUS LOW-K DIELECTRIC FILM AND FABRICATION METHOD THEREOF 审中-公开
    多孔低K电介质薄膜及其制造方法

    公开(公告)号：US20070173070A1

    公开(公告)日：2007-07-26

    申请号：US11307167

    申请日：2006-01-26

    申请人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

    发明人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

    IPC分类号： H01L21/31

    CPC分类号： H01L21/31695 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348

    摘要： A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogens in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.

    摘要翻译： 制造多孔低k电介质膜的方法包括提供基片，通过提供背骨前体以形成界面电介质层进行第一CVD工艺，通过提供致孔剂前体来形成背光源前体，进行第二CVD工艺， 骨层，并且去除背骨层中的致孔剂，使得背骨层变成超低k介电层。 界面电介质层和超低k电介质层组成多孔低k电介质膜。

    METHOD OF CURING POROUS LOW-K LAYER
    8.
    发明申请
    METHOD OF CURING POROUS LOW-K LAYER 审中-公开
    固化多孔低K层的方法

    公开(公告)号：US20080166498A1

    公开(公告)日：2008-07-10

    申请号：US11621812

    申请日：2007-01-10

    申请人： Mei-Ling Chen ,  Kuo-Chih Lai ,  Su-Jen Sung

    发明人： Mei-Ling Chen ,  Kuo-Chih Lai ,  Su-Jen Sung

    IPC分类号： B05D3/06

    CPC分类号： H01L21/31695 ,  B05D3/0209 ,  B05D3/067 ,  H01L21/02126 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31058

    摘要： A method of curing a porous low-k layer is described, which is applied to a substrate with a porous low-k layer formed thereon, wherein the porous low-k: layer contains a porogen. A first UV-curing treatment is performed to the porous low-k layer under a relatively milder condition, and then a second UV-curing treatment is performed to the porous low-k layer under a relatively harsher condition to finish the curing of the porous low-k layer.

    摘要翻译： 描述了一种固化多孔低k层的方法，其应用于其上形成有多孔低k层的基板，其中多孔低k层包含致孔剂。 在相对温和的条件下对多孔低k层进行第一次紫外线固化处理，然后在相对较苛刻的条件下对多孔低k层进行第二次UV固化处理，以完成多孔低k层的固化 低k层。

    FABRICATION METHOD OF POROUS LOW-K DIELECTRIC FILM
    9.
    发明申请
    FABRICATION METHOD OF POROUS LOW-K DIELECTRIC FILM 审中-公开
    多孔低K电介质膜的制造方法

    公开(公告)号：US20090275211A1

    公开(公告)日：2009-11-05

    申请号：US12503077

    申请日：2009-07-15

    申请人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

    发明人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

    IPC分类号： H01L21/316

    CPC分类号： H01L21/31695 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348

    摘要： A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogen material in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.

    摘要翻译： 制造多孔低k电介质膜的方法包括提供基片，通过提供背骨前体以形成界面电介质层进行第一CVD工艺，通过提供致孔剂前体来形成背光源前体，进行第二CVD工艺， 骨层，并且去除背骨层中的致孔剂材料，使得背骨层变成超低k电介质层。 界面电介质层和超低k电介质层组成多孔低k电介质膜。