公开(公告)号：US20090275211A1

公开(公告)日：2009-11-05

申请号：US12503077

申请日：2009-07-15

申请人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

发明人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

IPC分类号： H01L21/316

CPC分类号： H01L21/31695 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348

摘要： A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogen material in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.

摘要翻译： 制造多孔低k电介质膜的方法包括提供基片，通过提供背骨前体以形成界面电介质层进行第一CVD工艺，通过提供致孔剂前体来形成背光源前体，进行第二CVD工艺， 骨层，并且去除背骨层中的致孔剂材料，使得背骨层变成超低k电介质层。 界面电介质层和超低k电介质层组成多孔低k电介质膜。

公开(公告)号：US20070173070A1

公开(公告)日：2007-07-26

申请号：US11307167

申请日：2006-01-26

申请人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

发明人： Mei-Ling Chen ,  Su-Jen Sung ,  Kuo-Chih Lai ,  Jei-Ming Chen

IPC分类号： H01L21/31

CPC分类号： H01L21/31695 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348

摘要： A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogens in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.

摘要翻译： 制造多孔低k电介质膜的方法包括提供基片，通过提供背骨前体以形成界面电介质层进行第一CVD工艺，通过提供致孔剂前体来形成背光源前体，进行第二CVD工艺， 骨层，并且去除背骨层中的致孔剂，使得背骨层变成超低k介电层。 界面电介质层和超低k电介质层组成多孔低k电介质膜。

公开(公告)号：US20080026579A1

公开(公告)日：2008-01-31

申请号：US11459931

申请日：2006-07-25

申请人： Kuo-Chih Lai ,  Mei-Ling Chen ,  Jei-Ming Chen ,  Hsin-Hsing Chen ,  Shih-Feng Su ,  Meng-Chi Chen

发明人： Kuo-Chih Lai ,  Mei-Ling Chen ,  Jei-Ming Chen ,  Hsin-Hsing Chen ,  Shih-Feng Su ,  Meng-Chi Chen

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/02074 ,  H01L21/76883

摘要： A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the copper damascene process are removed by the heat treatment, therefore the copper damascene structure is completely reduced by the reduction plasma treatment and is improved.

摘要翻译： 铜镶嵌工艺包括提供其上具有介电层的基板，在介电层中至少形成铜镶嵌结构，对基板进行热处理，并对铜镶嵌结构的表面进行还原等离子体处理。 通过热处理除去在铜镶嵌工艺中形成的杂质，因此通过还原等离子体处理完全减少铜镶嵌结构并改善。

公开(公告)号：US07378343B2

公开(公告)日：2008-05-27

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/4763

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070111514A1

公开(公告)日：2007-05-17

申请号：US11164285

申请日：2005-11-17

申请人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

发明人： Jei-Ming Chen ,  Miao-Chun Lin ,  Kuo-Chih Lai ,  Mei-Ling Chen ,  Cheng-Ming Weng ,  Chun-Jen Huang ,  Yu-Tsung Lai

IPC分类号： H01L21/473

CPC分类号： H01L21/7681 ,  H01L21/76829

摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。

公开(公告)号：US20070077751A1

公开(公告)日：2007-04-05

申请号：US11163051

申请日：2005-10-03

申请人： Mei-Ling Chen ,  Jei-Ming Chen ,  Kuo-Chih Lai ,  Wen-Chieh Su

发明人： Mei-Ling Chen ,  Jei-Ming Chen ,  Kuo-Chih Lai ,  Wen-Chieh Su

IPC分类号： H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31695

摘要： A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to the low-k material to decrease the k-value thereof.

摘要翻译： 描述了一种将低k材料恢复的方法应用于其上具有低k材料的衬底，其中衬底已经经历提高低k材料的k值的先前工艺。 该方法包括对低k材料进行等离子体处理以降低其k值。

公开(公告)号：US20070218214A1

公开(公告)日：2007-09-20

申请号：US11308240

申请日：2006-03-14

申请人： Kuo-Chih Lai ,  Mei-Ling Chen ,  Jei-Ming Chen

发明人： Kuo-Chih Lai ,  Mei-Ling Chen ,  Jei-Ming Chen

IPC分类号： H05H1/00

CPC分类号： H01L21/31695 ,  H01L21/02074 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of improving adhesion property of a dielectric layer is provided. A dielectric layer is formed over a substrate. A plasma surface process comprising a plasma gas containing helium or hydrogen is performed to treat the surface of the dielectric layer. A cap layer is formed on the dielectric layer.

摘要翻译： 提供了提高电介质层的附着性的方法。 介电层形成在衬底上。 执行包括含有氦或氢的等离子体气体的等离子体表面处理以处理电介质层的表面。 在电介质层上形成盖层。

公开(公告)号：US20060281299A1

公开(公告)日：2006-12-14

申请号：US11462045

申请日：2006-08-03

申请人： Jei-Ming Chen ,  Chin-Hsiang Lin ,  Chih-Chien Liu ,  Kuo-Chih Lai

发明人： Jei-Ming Chen ,  Chin-Hsiang Lin ,  Chih-Chien Liu ,  Kuo-Chih Lai

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76849 ,  C23C16/0245 ,  C23C16/325 ,  H01L21/3148 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/48

摘要： A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.

摘要翻译： 准备覆盖衬底的电介质层。 镶嵌开口蚀刻到电介质层中。 镶嵌开口填充有铜或铜合金。 铜或铜合金的表面用含氢等离子体如H 2 N 3或NH 3 3等离子体处理。 然后在等离子体增强化学气相沉积（PECVD）条件下，铜或铜合金的处理表面与三甲基硅烷或三甲基硅烷反应。 随后，通过PECVD，将碳化硅层原位沉积在铜或铜合金上。

公开(公告)号：US20060199367A1

公开(公告)日：2006-09-07

申请号：US11164824

申请日：2005-12-07

申请人： Jim-Jey Huang ,  Chih-Chien Liu ,  Feng-Yu Hsu ,  Jei-Ming Chen ,  Kuo-Chih Lai

发明人： Jim-Jey Huang ,  Chih-Chien Liu ,  Feng-Yu Hsu ,  Jei-Ming Chen ,  Kuo-Chih Lai

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine to the film in-situ.

摘要翻译： 提供了互连的制造方法。 提供介电层。 在电介质层中形成金属层。 在电介质层上形成含氟阻挡层，覆盖金属层。 通过使用化学沉积方法形成含氟阻挡层，并将氟引入到膜中。

公开(公告)号：US20110065245A1

公开(公告)日：2011-03-17

申请号：US12558565

申请日：2009-09-13

申请人： Jei-Ming Chen ,  Kuo-Chih Lai ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

发明人： Jei-Ming Chen ,  Kuo-Chih Lai ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.

摘要翻译： 公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成栅极结构，在所述半导体衬底中与所述栅极结构的两侧相邻的源/漏区; 覆盖栅极结构和源极/漏极区域上的应力层; 蚀刻掉应力层以形成具有较大顶部和较小底部的多个开口以暴露栅极结构和源极/漏极区域的表面; 在开口中形成金属层; 并且使用应力层作为自对准硅化物块使金属层与栅极结构和源极/漏极区域反应以形成多个硅化物层。