公开(公告)号：US06057240A

公开(公告)日：2000-05-02

申请号：US55437

申请日：1998-04-06

申请人： Mei-Sheng Zhou ,  Jian-Hui Ye ,  Simon Chooi ,  Young-Tong Tsai

发明人： Mei-Sheng Zhou ,  Jian-Hui Ye ,  Simon Chooi ,  Young-Tong Tsai

IPC分类号： C11D1/04 ,  C11D1/68 ,  C11D1/70 ,  C11D3/30 ,  C11D11/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H05K3/06 ,  H01R13/502 ,  C11D9/00

CPC分类号： H01L21/02071 ,  B82Y10/00 ,  B82Y30/00 ,  C11D11/0047 ,  C11D3/30 ,  H01L21/31138 ,  H01L21/32136 ,  H05K3/064 ,  C11D1/04 ,  H05K2203/0793 ,  H05K2203/095

摘要： A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer. There is then stripped from the sidewall of the patterned metal layer the oxidized metal impregnated polymer residue layer while employing an aqueous alkyl ammonium hydroxide based solution. The aqueous alkyl ammonium hydroxide based solution has incorporated therein a surfactant capable of forming a monolayer adsorbed upon the sidewall of the patterned metal layer.

摘要翻译： 一种用于在微电子制造中形成图案化金属层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成覆盖金属层。 然后在覆盖金属层上形成图案化的光致抗蚀剂层。 然后通过使用等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为光刻胶蚀刻掩模层，覆盖金属层以形成图案化的金属层。 如此形成的图案化金属层具有形成在图案化金属层的侧壁上的金属浸渍碳质聚合物残余层。 然后通过使用含氧等离子体从图案化的金属层剥离图案化的光刻胶层，同时对金属浸渍的碳质聚合物残余层进行氧化，以在图案化金属层的侧壁上形成氧化金属浸渍的聚合物残余物层。 然后从图案化金属层的侧壁剥离氧化金属浸渍的聚合物残余物层，同时使用基于烷基氢氧化铵的水溶液。 基于烷基氢氧化铵的水溶液溶液中加入了能够形成单层吸附在图案化金属层的侧壁上的表面活性剂。

公开(公告)号：US6009888A

公开(公告)日：2000-01-04

申请号：US73946

申请日：1998-05-07

申请人： Jian-Hui Ye ,  Yuan-Ping Lee ,  Mei-Sheng Zhou ,  Yong-Feng Lu

发明人： Jian-Hui Ye ,  Yuan-Ping Lee ,  Mei-Sheng Zhou ,  Yong-Feng Lu

IPC分类号： B08B7/00 ,  G03F7/42 ,  H01L21/311 ,  B08B7/04

CPC分类号： H01L21/31127 ,  B08B7/0042 ,  G03F7/423 ,  H01L21/31133

摘要： A method of stripping photoresist and polymer from a wafer after a dry etch of a nitrade or a polysilicon layer that immerses the wafer in a peroxydisulfate (S.sub.2 O.sub.8.sup.2-)/HCl wet bath and while the wafer is still immersed, irradiates the wafer with a UV laser. The method comprises: (a) forming an silicon nitride layer 24 and a photoresist pattern 28 over a semi conductor structure 10; (b) dry etching the silicon nitride layer 24 thus forming a polymer 30 over the photoresist pattern, and the silicon nitride layer, (c) Immersing the substrate, the photoresist pattern, the polymer 30 in a liquid bath 34 comprising (1) peroxydisulfate (S.sub.2 O.sub.8.sup.2-), (2) HCl, and (3) water; and irradiating the photoresist pattern 28 and polymer layer 30 with a UV laser thereby removing the photoresist 28 and polymer 30.

摘要翻译： 在将晶片浸入过氧二硫酸盐（S2O82-）/ HCl湿浴中并在晶片仍然浸没之后的氮化或多晶硅层的干蚀刻之后，从晶片剥离光致抗蚀剂和聚合物的方法， 激光。 该方法包括：（a）在半导体结构10上形成氮化硅层24和光致抗蚀剂图案28; （b）干蚀刻氮化硅层24，从而在光致抗蚀剂图案和氮化硅层上形成聚合物30，（c）将基底，光致抗蚀剂图案，聚合物30浸入液浴34中，该液槽34包括（1）过氧化二硫酸 （S2O82-），（2）HCl和（3）水; 并用UV激光照射光致抗蚀剂图案28和聚合物层30，从而除去光致抗蚀剂28和聚合物30。

公开(公告)号：US06358842B1

公开(公告)日：2002-03-19

申请号：US09633770

申请日：2000-08-07

申请人： Mei-Sheng Zhou ,  Simon Chooi ,  Yi Xu

发明人： Mei-Sheng Zhou ,  Simon Chooi ,  Yi Xu

IPC分类号： H01L213205

CPC分类号： H01L21/76831 ,  H01L21/31138 ,  H01L21/76808

摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.

摘要翻译： 已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。 镶嵌互连可以是单镶嵌或双镶嵌。 提供铜导体覆盖在半导体衬底上。 第一钝化层被提供在铜导体上。 沉积在第一钝化层上的低介电常数层。 沉积覆盖在低介电常数层上的可选的覆盖层。 沉积在覆盖层上的光致抗蚀剂层。 覆盖层和低介电常数层被蚀刻通过以形成通孔。 同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。 从而防止侧壁弯曲和通过中毒。 蚀刻第一钝化层以暴露下面的铜导体。 沉积覆盖覆盖层并填充通孔的铜层。 铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

公开(公告)号：US06350675B1

公开(公告)日：2002-02-26

申请号：US09686282

申请日：2000-10-12

申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。 本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。 在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于 抗蚀剂层。 提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。 该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

公开(公告)号：US06835989B2

公开(公告)日：2004-12-28

申请号：US10736943

申请日：2003-12-16

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。 此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06475908B1

公开(公告)日：2002-11-05

申请号：US09981415

申请日：2001-10-18

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2144

CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06429122B2

公开(公告)日：2002-08-06

申请号：US09925820

申请日：2001-08-10

申请人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

发明人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831

摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

公开(公告)号：US06352917B1

公开(公告)日：2002-03-05

申请号：US09598691

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L21/76885 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

摘要翻译： 已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。 该方法创建一个反向的双镶嵌结构。 第一电介质层设置在半导体衬底上。 图案化电介质层以形成用于计划的大马士革互连的沟槽。 可以可选地在沟槽侧壁上形成绝缘间隔物。 导电阻挡层沉积在电介质层上并衬在沟槽上。 沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。 金属层和导电阻挡层被抛光，从而形成镶嵌互连。 可以任选地沉积钝化层。 大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。 图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。 在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

公开(公告)号：US06225202B1

公开(公告)日：2001-05-01

申请号：US09598689

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  C23F4/00 ,  H01L21/32136

摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.

摘要翻译： 描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。 在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。 在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。 在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。 半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。 将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

公开(公告)号：US06677652B2

公开(公告)日：2004-01-13

申请号：US10227697

申请日：2002-08-26

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.