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    Flash memory programming and verification with reduced leakage current
    4.
    发明授权
    Flash memory programming and verification with reduced leakage current 有权
    闪存编程和验证，减少漏电流

    公开(公告)号：US07630253B2

    公开(公告)日：2009-12-08

    申请号：US11398415

    申请日：2006-04-05

    申请人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    发明人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

    摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

    摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

    Method for determining wordline critical dimension in a memory array and related structure
    5.
    发明授权
    Method for determining wordline critical dimension in a memory array and related structure 有权
    用于确定存储器阵列和相关结构中的字线临界尺寸的方法

    公开(公告)号：US07339222B1

    公开(公告)日：2008-03-04

    申请号：US11416551

    申请日：2006-05-03

    申请人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

    发明人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

    IPC分类号： H01L27/108

    CPC分类号： H01L27/115 ,  H01L27/11517 ,  Y10S257/905

    摘要： According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

    摘要翻译： 根据一个示例性实施例，一种用于制造存储器阵列的方法包括在衬底中形成多个沟槽，其中沟槽确定衬底中的多个字线区域，其中每个字线区域位于两个相邻的沟槽之间，以及 其中每个字线区域具有字线区域宽度。 存储器阵列可以是闪存阵列。 该方法还包括在衬底中形成多个位线，其中位线垂直于沟槽定位。 该方法还包括在每个沟槽中形成电介质区域。 该方法还包括在位线，字线区域和沟槽之间形成电介质叠层。 该方法还包括形成多个字线，其中每个字线位于一个字线区域上。 字线区域宽度决定每个字线的有效字线宽度。

    Read-only memory array with dielectric breakdown programmability
    6.
    发明申请
    Read-only memory array with dielectric breakdown programmability 审中-公开
    具有介电击穿可编程性的只读存储阵列

    公开(公告)号：US20060268593A1

    公开(公告)日：2006-11-30

    申请号：US11136981

    申请日：2005-05-25

    申请人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    发明人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/118

    摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.

    摘要翻译： 根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。 可编程ROM阵列还包括位于至少一个位线上的至少一个字线。 可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。 通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。 编程操作使存储单元作为二极管工作。 可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

    Flash memory programming and verification with reduced leakage current
    7.
    发明授权
    Flash memory programming and verification with reduced leakage current 有权
    闪存编程和验证，减少漏电流

    公开(公告)号：US08031528B2

    公开(公告)日：2011-10-04

    申请号：US12557721

    申请日：2009-09-11

    申请人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    发明人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

    摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

    摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

    Memory cell having enhanced high-K dielectric
    9.
    发明授权
    Memory cell having enhanced high-K dielectric 有权
    具有增强的高K电介质的存储单元

    公开(公告)号：US07365389B1

    公开(公告)日：2008-04-29

    申请号：US11008233

    申请日：2004-12-10

    申请人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

    发明人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

    IPC分类号： H01L29/792

    CPC分类号： H01L29/513 ,  H01L29/792

    摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

    摘要翻译： 半导体存储器件可以包括介于电荷存储层和控制栅之间的高K，高势垒高电介质材料的隔间电介质层。 利用这种隔间高K，高势垒高电介质就位，可以使用Fowler-Nordheim隧道有效地擦除存储器件。

    Flash memory programming and verification with reduced leakage current
    10.
    发明申请
    Flash memory programming and verification with reduced leakage current 有权
    闪存编程和验证，减少漏电流

    公开(公告)号：US20070237003A1

    公开(公告)日：2007-10-11

    申请号：US11398415

    申请日：2006-04-05

    申请人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    发明人： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

    摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

    摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。