公开(公告)号：US12224271B2

公开(公告)日：2025-02-11

申请号：US17193871

申请日：2021-03-05

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: H01L27/15 ,  G06F1/16 ,  H01L21/683 ,  H01L25/075 ,  H01L25/16 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L33/52 ,  H01L33/62 ,  G02B27/01

Abstract: In some examples, an article comprises a semiconductor including at least one integrated circuit, a μLED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the μLED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor.

公开(公告)号：US11668942B2

公开(公告)日：2023-06-06

申请号：US17686295

申请日：2022-03-03

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: G02B27/01 ,  G03F7/00 ,  G02B6/32 ,  G02B27/30

CPC classification number: G02B27/0172 ,  G02B6/32 ,  G03F7/0002 ,  G02B27/30

Abstract: Disclosed herein are techniques for aligning a collimator assembly with an array of LEDs and apparatuses formed using the disclosed techniques. According to certain embodiments, a display projector includes a display device and a collimator assembly. The display device includes a backplane including a first plurality of features. The display device further includes a plurality of dies. Each die of the plurality of dies comprises a plurality of light emitting diodes and is bonded to the backplane. The collimator assembly includes a plurality of lenses and a second plurality of features. The collimator assembly is attached to the display device through coupling the first plurality of features with the second plurality of features such that the plurality of dies are aligned with the plurality of lenses.

公开(公告)号：US11545475B2

公开(公告)日：2023-01-03

申请号：US17318736

申请日：2021-05-12

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L25/075 ,  H01L33/62

Abstract: An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

公开(公告)号：US20250125322A1

公开(公告)日：2025-04-17

申请号：US19000405

申请日：2024-12-23

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: H01L25/16 ,  G02B27/01 ,  G06F1/16 ,  H01L21/683 ,  H01L25/075 ,  H10H20/01 ,  H10H20/852 ,  H10H20/857

Abstract: Systems and devices describe an augmented-reality glasses having a plurality of panels of light emitters arranged to form an array of light emitters, collimation optics for collimating light received from the array of light emitters, an optical coupler for receiving the collimated light, and a waveguide for display of augmented-reality content to a wearer of the augmented-reality glasses. In some embodiments, the array of light emitters includes light emitters generating three colors, each panel of the plurality of panels of light emitters having light emitters generating a same color, and each panel of the plurality of panels of light emitters positioned on a surface of a semiconductor with at least one integrated circuit. The array of light emitters can be two-dimensional array of light emitters arranged on a common plane and characterized by a pitch that is less than 2 μm.

公开(公告)号：US20240274587A1

公开(公告)日：2024-08-15

申请号：US18401185

申请日：2023-12-29

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse ,  Ronald Ho ,  Maryam Rahimi ,  Janani Chandrasekhar ,  Jaesik Lee ,  Aswani Kurra

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/16 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16225

Abstract: A circuit assembly may include a first sub-package a first chiplet including an active frontside that includes active circuitry and faces in a first direction, a second sub-package including a second chiplet including an active frontside that includes active circuitry and faces in a second direction opposite the first direction, and a memory sub-package including a memory. The first sub-package, the second sub-package, and the memory sub-package may be arranged so as to overlap each other in the first direction. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US11852835B2

公开(公告)日：2023-12-26

申请号：US18062409

申请日：2022-12-06

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: G02B27/01 ,  G06T19/00 ,  H10B10/00

CPC classification number: G02B27/0176 ,  G06T19/006 ,  H10B10/00

Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

公开(公告)号：US20240332260A1

公开(公告)日：2024-10-03

申请号：US18617001

申请日：2024-03-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Sunil Gupta ,  Rajendra D. Pendse

IPC: H01L25/065 ,  G06V10/94 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L25/105 ,  G06V10/94 ,  H01L2224/08145 ,  H01L2224/16225

Abstract: An artificial-reality system including (1) an output device, (2) one or more real-world sensors, and (3) an integrated-circuit package including (A) a general-purpose system-on-chip having a first die-to-die interface and (B) a differentiated artificial-reality task-specific chiplet having a second die-to-die interface coupled to the first die-to-die interface of the general-purpose system-on-chip. The differentiated artificial-reality task-specific chiplet may be configured to generate an output by performing one or more differentiated artificial-reality processing tasks on one or more inputs derived from the one or more real-world sensors, and the general-purpose system-on-chip may be configured to present, via the output device, an artificial reality to a user based at least in part on the output of the differentiated artificial-reality task-specific chiplet. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US20240241231A1

公开(公告)日：2024-07-18

申请号：US18391655

申请日：2023-12-21

Applicant: Meta Platforms Technologies, LLC

Inventor： Jack Diepen Mumbo ,  Rajendra D. Pendse ,  Alexandra Gualdino ,  Jaspreet Singh Gandhi ,  Jeremiah Nyaribo ,  Harish Venkataraman ,  Gregory Cohoon

IPC: G01S7/4865 ,  G01S7/481 ,  G01S17/10 ,  H01L23/00 ,  H01L31/107

CPC classification number: G01S7/4865 ,  G01S7/4811 ,  G01S17/10 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L31/107 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/73207 ,  H01L2924/12041

Abstract: A time-of-flight (ToF) module includes a light source, a driver module, and a light sensor. The driver module includes electrical circuitry configured to selectively drive the light source to emit pulsed illumination light. The light sensor is configured to sense returning light reflected from a target. At least one of the light source, driver module, and light sensor is stacked on another to reduce a footprint of the ToF module.

公开(公告)号：US11550158B2

公开(公告)日：2023-01-10

申请号：US16910792

申请日：2020-06-24

Applicant: Meta Platforms Technologies, LLC

Inventor： Rajendra D. Pendse

IPC: G02B27/01 ,  G06T19/00 ,  H01L27/11

Abstract: Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

公开(公告)号：US20220407987A1

公开(公告)日：2022-12-22

申请号：US17843117

申请日：2022-06-17

Applicant: Meta Platforms Technologies, LLC

Inventor： Chao Han ,  Eddie Alex Azuma ,  Manoj Bikumandla ,  Rajendra D. Pendse ,  Cina Hazegh

IPC: H04N5/225 ,  H04N5/232

Abstract: A camera module includes an image sensor, a lens assembly, a printed circuit board, and a substrate. The image sensor has edges that define a two-dimensional footprint substantially parallel to a surface of the image sensor. The lens assembly is coupled to a top surface of the image sensor and focuses light onto the top surface of the image sensor. Edges of the lens assembly do not extend beyond the footprint. The printed circuit board is below the image sensor and controls the image sensor. The substrate is coupled to a bottom surface of the image sensor and to a top surface of the printed circuit board. The substrate electrically couples the image sensor to the printed circuit board. Edges of the substrate do not extend beyond the footprint.