公开(公告)号：US07160793B2

公开(公告)日：2007-01-09

申请号：US11066408

申请日：2005-02-25

申请人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

发明人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

IPC分类号： H01L21/47

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811

摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

摘要翻译： RESURF沟槽栅极MOSFET具有足够小的间距（相邻沟槽的紧密间隔），漏极漂移区的中间区域在MOSFET的阻塞状态下耗尽。 然而，在已知的器件结构中，在有源器件区域的周边/边缘处和/或与栅极接合焊盘相邻处，仍然会发生过早击穿。 为了防止过早击穿，本发明采用两个原则：栅极接合板或者连接到由有源单元包围的底层条纹沟槽网络，或者直接位于有源单元的顶部，并且在RESURF周围提供兼容的2D边缘终端方案 有源设备区域。 这些原理可以在各种蜂窝布局中实现，例如。 在活动区域​​和边缘终止中可以是圆形或矩形或椭圆形的同心环形装置几何形状，或者这种同心六边形或圆形条纹细胞的装置阵列，或具有条纹边缘细胞的方形活性细胞的装置阵列 ，或具有六边形边缘单元的边缘终止的六边形活性单元的器件阵列。

公开(公告)号：US07235842B2

公开(公告)日：2007-06-26

申请号：US10564214

申请日：2003-07-12

申请人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

发明人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238

摘要： A trench-gate semiconductor device (100) has a trench network (STR1, ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.

摘要翻译： 沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1，ITR1）。 沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR 1）和晶体管单元的相邻角的交叉沟槽区域（ITR 1）。 如图所示。 图16是沿图1的II-II线的剖视图。 如图11所示，交点沟槽区域（ITR 1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于绝缘材料（21B 1）的底部的厚度 段沟槽区域（STR 1）。 从交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）的较大厚度对于增加器件（100）的漏 - 源反向击穿电压是有效的。 从每个交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道的垂直方向的至少一部分的至少部分的细胞（TCS）上增厚绝缘材料， 容纳体区域（23），以增加装置的阈值电压。

公开(公告)号：US07262460B2

公开(公告)日：2007-08-28

申请号：US10538216

申请日：2003-12-08

申请人： Jurriaan Schmitz ,  Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Andreas H. Montree ,  Michael A. A. In't Zandt ,  Gerrit E. J. Koops

发明人： Jurriaan Schmitz ,  Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Andreas H. Montree ,  Michael A. A. In't Zandt ,  Gerrit E. J. Koops

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.

摘要翻译： 通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。 使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在 所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

公开(公告)号：US06833583B2

公开(公告)日：2004-12-21

申请号：US10238795

申请日：2002-09-10

申请人： Michael A. A. In't Zandt ,  Erwin A. Hijzen ,  Raymond J. E. Hueting

发明人： Michael A. A. In't Zandt ,  Erwin A. Hijzen ,  Raymond J. E. Hueting

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： To avoid premature breakdown at the edge of the active area of RESURF trench-gate MOS device, an edge field plate (24) can be placed with a connection to the gate and a second spaced field plate (24) in the same trench (12). The gate trench network (12) could be either formed by hexagon unit cells or by square unit cells. Since the RESURF condition requires a small cell pitch, self-aligned processing could be used.

摘要翻译： 为了避免在RESURF沟槽栅极MOS器件的有源区域的边缘处的过早击穿，边缘场板（24）可以通过与栅极的连接和在相同沟槽（12）中的第二间隔的场板（24）放置 ）。 栅极沟槽网络（12）可以由六边形单元电池或方形单元电池形成。 由于RESURF条件需要较小的单元间距，因此可以使用自对准处理。

公开(公告)号：US07332398B2

公开(公告)日：2008-02-19

申请号：US10538214

申请日：2003-12-08

申请人： Michael A. A. In't Zandt ,  Erwin A. Hijzen

发明人： Michael A. A. In't Zandt ,  Erwin A. Hijzen

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518

摘要： A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches (20), the steps of: (a) forming a silicon oxide layer (21) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon (31) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers (32) on the doped polysilicon (21) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation (33) at the trench bottoms; (e) removing the silicon nitride spacers (32); and (f) depositing gate conductive material (34) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation (33) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon (31) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.

摘要翻译： 一种制造沟槽栅极半导体器件（1）的方法，所述方法包括在器件的有源晶体管单元区域中的半导体本体（10）中形成沟槽（20），所述沟槽（20）各自具有沟槽底部和 沟槽侧壁，并且在沟槽中提供氧化硅栅极绝缘体（21），使得在沟槽底部处的栅极绝缘体（33）比沟槽侧壁处的栅极绝缘体（21）更厚，以便降低栅极 - 漏极电容 装置。 该方法包括在形成沟槽（20）之后的步骤：（a）在沟槽底部和沟槽侧壁处形成氧化硅层（21）; （b）在沟槽底部和沟槽侧壁附近沉积一层掺杂多晶硅（31）; （c）在与沟槽侧壁相邻的掺杂多晶硅（21）上形成氮化硅间隔物（32），留下在沟槽底部暴露的掺杂多晶硅; （d）热氧化暴露的掺杂多晶硅以在沟槽底部生长所述较厚的栅极绝缘体（33）; （e）去除氮化硅间隔物（32）; 和（f）在所述沟槽内淀积栅极导电材料（34）以形成所述器件的栅电极。 沟槽底部较厚的栅极绝缘体（33）的最终厚度由步骤（b）中沉积的掺杂多晶硅层（31）的厚度很好地控制。 此外，掺杂（优选大于5埃19厘米3）的多晶硅在低温（优选700-800℃）下快速氧化，降低了在该阶段存在于器件中的扩散（例如p体）植入的风险。

公开(公告)号：US07199010B2

公开(公告)日：2007-04-03

申请号：US10538212

申请日：2003-12-08

申请人： Erwin A. Hijzen ,  Raymond J. E. Hueting ,  Michael A. A. In't Zandt

发明人： Erwin A. Hijzen ,  Raymond J. E. Hueting ,  Michael A. A. In't Zandt

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/518

摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

摘要翻译： 制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。 然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。 这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

公开(公告)号：US06956264B2

公开(公告)日：2005-10-18

申请号：US10308656

申请日：2002-12-03

申请人： Erwin A. Hijzen ,  Michael A. A. In't Zandt ,  Raymond J. E. Hueting

发明人： Erwin A. Hijzen ,  Michael A. A. In't Zandt ,  Raymond J. E. Hueting

IPC分类号： H01L29/41 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/872 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/28211 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/872

摘要： In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

摘要翻译： 在包括沟槽（20）中的绝缘沟槽电极（11）的半导体器件中，例如沟槽栅场效应功率晶体管和沟槽肖特基二极管，在沟槽的底部（25）之间提供空腔（23） 电极（11）和沟槽（20）的底部（27），以紧凑的方式减小沟槽电极（11）和沟槽底部（27）处的主体部分之间的电介质耦合。 在功率晶体管中，介电耦合的减小降低了开关功率损耗，而在肖特基二极管中，能够减小沟槽宽度。

公开(公告)号：US06936890B2

公开(公告)日：2005-08-30

申请号：US10236175

申请日：2002-09-06

申请人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

发明人： Raymond J. E. Hueting ,  Erwin A. Hijzen ,  Michael A. A. In't Zandt

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811

摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

摘要翻译： RESURF沟槽栅极MOSFET具有足够小的间距（相邻沟槽的紧密间隔），漏极漂移区的中间区域在MOSFET的阻塞状态下耗尽。 然而，在已知的器件结构中，在有源器件区域的周边/边缘处和/或与栅极接合焊盘相邻处，仍然会发生过早击穿。 为了防止过早击穿，本发明采用两个原则：栅极接合板或者连接到由有源单元包围的底层条纹沟槽网络，或者直接位于有源单元的顶部，并且在RESURF周围提供兼容的2D边缘终端方案 有源设备区域。 这些原理可以在各种蜂窝布局中实现，例如。 在活动区域​​和边缘终止中可以是圆形或矩形或椭圆形的同心环形装置几何形状，或这种同心六边形或圆形条纹细胞的装置阵列，或具有条纹边缘细胞的方形活性细胞的装置阵列 ，或具有六边形边缘单元的边缘终止的六边形活性单元的器件阵列。