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    STI formation in semiconductor device including SOI and bulk silicon regions
    1.
    发明授权
    STI formation in semiconductor device including SOI and bulk silicon regions 有权
    在包括SOI和体硅区域的半导体器件中形成STI

    公开(公告)号：US07394131B2

    公开(公告)日：2008-07-01

    申请号：US11425467

    申请日：2006-06-21

    申请人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    发明人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    IPC分类号： H01L27/01

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    STI formation in semiconductor device including SOI and bulk silicon regions
    2.
    发明授权
    STI formation in semiconductor device including SOI and bulk silicon regions 失效
    在包括SOI和体硅区域的半导体器件中形成STI

    公开(公告)号：US07118986B2

    公开(公告)日：2006-10-10

    申请号：US10710060

    申请日：2004-06-16

    申请人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    发明人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    IPC分类号： H01L21/76

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，同时在SOI和体硅区域中蚀刻STI，进行蚀刻到体硅区域中期望深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    SEMICONDUCTOR ETCHING METHODS
    5.
    发明申请
    SEMICONDUCTOR ETCHING METHODS 审中-公开
    半导体蚀刻方法

    公开(公告)号：US20090047791A1

    公开(公告)日：2009-02-19

    申请号：US11839681

    申请日：2007-08-16

    申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L27/10844 ,  H01L27/11

    摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

    摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

    Vertical SOI trench SONOS cell
    6.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US07514323B2

    公开(公告)日：2009-04-07

    申请号：US11164513

    申请日：2005-11-28

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/00

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Vertical SOI trench SONOS cell
    7.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US08008713B2

    公开(公告)日：2011-08-30

    申请号：US12410935

    申请日：2009-03-25

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/00

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    VERTICAL SOI TRENCH SONOS CELL
    8.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20090158234A1

    公开(公告)日：2009-06-18

    申请号：US11955913

    申请日：2007-12-13

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： G06F17/50

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

    摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。 特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中产生垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物 - 半导体（SONOS）存储单元的半导体存储器件，其允许将 基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    VERTICAL SOI TRENCH SONOS CELL
    9.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20090224308A1

    公开(公告)日：2009-09-10

    申请号：US12410935

    申请日：2009-03-25

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Vertical SOI trench SONOS cell
    10.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US07893485B2

    公开(公告)日：2011-02-22

    申请号：US11955913

    申请日：2007-12-13

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

    摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。 特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元的半导体存储器件，其允许将 基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。