利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

61 条记录 (耗时 0.03 秒)

    SEMICONDUCTOR ETCHING METHODS
    1.
    发明申请
    SEMICONDUCTOR ETCHING METHODS 审中-公开
    半导体蚀刻方法

    公开(公告)号：US20090047791A1

    公开(公告)日：2009-02-19

    申请号：US11839681

    申请日：2007-08-16

    申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L27/10844 ,  H01L27/11

    摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

    摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

    STI formation for vertical and planar transistors
    3.
    发明授权
    STI formation for vertical and planar transistors 有权
    垂直和平面晶体管的STI形成

    公开(公告)号：US06893938B2

    公开(公告)日：2005-05-17

    申请号：US10419588

    申请日：2003-04-21

    申请人： Munir D. Naeem ,  Hiroyuki Akatsu ,  Byeong Kim ,  Rolf Weis ,  David Mark Dobuzinksy ,  Johnathan E. Faltermeier

    发明人： Munir D. Naeem ,  Hiroyuki Akatsu ,  Byeong Kim ,  Rolf Weis ,  David Mark Dobuzinksy ,  Johnathan E. Faltermeier

    IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76232 ,  H01L21/3081

    摘要： A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

    摘要翻译： 一种用于形成用于半导体器件的浅沟槽隔离（STI）的方法。 第一硬掩模沉积在半导体晶片上，并且第二硬掩模沉积在第一硬掩模上。 半导体晶片包括第一蚀刻区和设置在第一蚀刻区下方的至少第二蚀刻区。 选择用于第一蚀刻区域的蚀刻工艺和用于至少一个第二蚀刻区域的蚀刻工艺，使得在半导体器件内形成平滑的侧壁表面结构。 每个后续蚀刻区域的蚀刻工艺可以在非选择性和选择性蚀刻工艺之间交替，以至少保留第一硬掩模材料。

    STI formation in semiconductor device including SOI and bulk silicon regions
    4.
    发明授权
    STI formation in semiconductor device including SOI and bulk silicon regions 有权
    在包括SOI和体硅区域的半导体器件中形成STI

    公开(公告)号：US07394131B2

    公开(公告)日：2008-07-01

    申请号：US11425467

    申请日：2006-06-21

    申请人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    发明人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    IPC分类号： H01L27/01

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    STI formation in semiconductor device including SOI and bulk silicon regions
    5.
    发明授权
    STI formation in semiconductor device including SOI and bulk silicon regions 失效
    在包括SOI和体硅区域的半导体器件中形成STI

    公开(公告)号：US07118986B2

    公开(公告)日：2006-10-10

    申请号：US10710060

    申请日：2004-06-16

    申请人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    发明人： Michael D. Steigerwalt ,  Mahender Kumar ,  Herbert L. Ho ,  David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Denise Pendleton

    IPC分类号： H01L21/76

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，同时在SOI和体硅区域中蚀刻STI，进行蚀刻到体硅区域中期望深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS
    6.
    发明申请
    TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开
    具有仅一个方向的横向延伸的TRENCH电容器及相关方法

    公开(公告)号：US20070267671A1

    公开(公告)日：2007-11-22

    申请号：US11383861

    申请日：2006-05-17

    申请人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Paul C. Parries ,  William C. Wille

    发明人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Paul C. Parries ,  William C. Wille

    IPC分类号： H01L29/94

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.

    摘要翻译： 公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。 在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。 横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。

    FinFET spacer formation by oriented implantation
    7.
    发明授权
    FinFET spacer formation by oriented implantation 有权
    FinFET间隔物通过定向植入形成

    公开(公告)号：US08716797B2

    公开(公告)日：2014-05-06

    申请号：US12611444

    申请日：2009-11-03

    申请人： Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

    发明人： Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

    摘要： A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

    摘要翻译： 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

    Stress enhanced transistor devices and methods of making
    9.
    发明授权
    Stress enhanced transistor devices and methods of making 有权
    应力增强晶体管器件和制造方法

    公开(公告)号：US08216893B2

    公开(公告)日：2012-07-10

    申请号：US12691170

    申请日：2010-01-21

    申请人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    发明人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7849 ,  H01L29/66636 ,  H01L29/78

    摘要： Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

    摘要翻译： 公开了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：通过栅极电介质在半导体衬底上方间隔开的栅极导体，其中半导体衬底包括在栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中沟道区域包括 栅极导体下方的底切区域; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。

    DRAM having deep trench capacitors with lightly doped buried plates
    10.
    发明授权
    DRAM having deep trench capacitors with lightly doped buried plates 有权
    DRAM具有具有轻掺杂掩埋板的深沟槽电容器

    公开(公告)号：US07923815B2

    公开(公告)日：2011-04-12

    申请号：US11969986

    申请日：2008-01-07

    申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

    摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

    摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。