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    SEMICONDUCTOR ETCHING METHODS
    1.
    发明申请
    SEMICONDUCTOR ETCHING METHODS 审中-公开
    半导体蚀刻方法

    公开(公告)号：US20090047791A1

    公开(公告)日：2009-02-19

    申请号：US11839681

    申请日：2007-08-16

    申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L27/10844 ,  H01L27/11

    摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

    摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

    TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS
    3.
    发明申请
    TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开
    具有仅一个方向的横向延伸的TRENCH电容器及相关方法

    公开(公告)号：US20070267671A1

    公开(公告)日：2007-11-22

    申请号：US11383861

    申请日：2006-05-17

    申请人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Paul C. Parries ,  William C. Wille

    发明人： Kangguo Cheng ,  Lisa F. Edge ,  Johnathan E. Faltermeier ,  Paul C. Parries ,  William C. Wille

    IPC分类号： H01L29/94

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.

    摘要翻译： 公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。 在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。 横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。

    Resist formulation which minimizes blistering during etching
    4.
    发明授权
    Resist formulation which minimizes blistering during etching 失效
    抗蚀剂制剂，其最小化蚀刻期间的起泡

    公开(公告)号：US06207353B1

    公开(公告)日：2001-03-27

    申请号：US08987808

    申请日：1997-12-10

    申请人： Michael D. Armacost ,  Willard E. Conley ,  Tina J. Cotler-Wagner ,  Ronald A. DellaGuardia ,  David M. Dobuzinsky ,  Michael L. Passow ,  William C. Wille

    发明人： Michael D. Armacost ,  Willard E. Conley ,  Tina J. Cotler-Wagner ,  Ronald A. DellaGuardia ,  David M. Dobuzinsky ,  Michael L. Passow ,  William C. Wille

    IPC分类号： G03F700

    CPC分类号： H01L21/0274 ,  G03F7/039 ,  H01L21/31116 ,  H01L21/31144

    摘要： A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer. Preferably, the terpolymer is made up of about 70% 4-hydroxystyrene, about 20% styrene, and about 10% t-butylacrylate.

    摘要翻译： 抗蚀剂制剂使反应离子蚀刻过程中的起泡最小化，导致聚合物副产物沉积量增加。 这种方法包括以足够的能量激发气态碳氟化合物蚀刻剂以形成高密度等离子体，以及使用碳 - 氟比至少为0.33的蚀刻剂。 除了常规的光活性组分之外，在这些条件下使泡沫最小化的抗蚀剂包括具有以下三元共聚物的树脂粘合剂：（a）含有酸不稳定基团的单元; （b）不含反应性基团和羟基的单元; 和（c）有助于光致抗蚀剂的水性显影性的单元。 在氧化硅层上形成光致抗蚀剂并形成高密度等离子体之后，将高密度等离子体引入到氧化硅层中以蚀刻氧化硅层中的至少一个开口。 优选地，三元共聚物由约70％的4-羟基苯乙烯，约20％的苯乙烯和约10％的丙烯酸叔丁酯组成。

    Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme
    6.
    发明授权
    Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme 失效
    各向异性氮化物蚀刻工艺，在镶嵌蚀刻方案中对氧化物和光致抗蚀剂层具有高选择性

    公开(公告)号：US06461529B1

    公开(公告)日：2002-10-08

    申请号：US09299137

    申请日：1999-04-26

    申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Waldemar W. Kocon ,  William C. Wille ,  Richard Wise

    发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Waldemar W. Kocon ,  William C. Wille ,  Richard Wise

    IPC分类号： H01L213215

    CPC分类号： H01L29/66583 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823481

    摘要： A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The etchant gas can be used during a nitride etch step in a process for making a metal oxide semiconductor field effect transistor.

    摘要翻译： 一种用于各向异性蚀刻多层结构的氮化硅层中的沟槽的工艺和蚀刻剂气体组合物。 蚀刻剂气体组合物具有包括聚合剂，氢源，氧化剂和惰性气体稀释剂的蚀刻剂气体。 氧化剂优选包括含碳氧化剂组分和氧化剂 - 惰性气体组分。 碳氟化合物气体选自CF4，C2F6和C3F8; 氢源选自CHF 3，CH 2 F 2，CH 3 F和H 2; 氧化剂选自CO，CO 2和O 2; 惰性气体稀释剂选自He，Ar和Ne。 添加成分以达到对氧化硅和光致抗蚀剂具有高氮化物选择性的蚀刻剂气体。 将诸如RF电源的电源施加到结构以控制通过激发蚀刻剂气体形成的高密度等离子体的方向性。 控制等离子体方向性的电源与用于激发蚀刻剂气体的电源脱耦。 在制造金属氧化物半导体场效应晶体管的工艺中的氮化物蚀刻步骤期间可以使用蚀刻剂气体。

    STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE
    7.
    发明申请
    STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中形成改进隔离的结构和方法

    公开(公告)号：US20080171420A1

    公开(公告)日：2008-07-17

    申请号：US11622057

    申请日：2007-01-11

    申请人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

    发明人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/76227 ,  H01L21/76237

    摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

    摘要翻译： 公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。 衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。 硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。 在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

    Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material
    8.
    发明授权
    Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material 有权
    使用与扩散阻挡材料耦合的平面化材料形成镶嵌结构的方法

    公开(公告)号：US07030031B2

    公开(公告)日：2006-04-18

    申请号：US10604056

    申请日：2003-06-24

    申请人： William C. Wille ,  Daniel C. Edelstein ,  William J. Cote ,  Peter E. Biolsi ,  John Fritche ,  Allan W. Upham

    发明人： William C. Wille ,  Daniel C. Edelstein ,  William J. Cote ,  Peter E. Biolsi ,  John Fritche ,  Allan W. Upham

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

    摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

    摘要翻译： 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein
    10.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein 有权
    形成具有离子固化电绝缘层的集成电路器件的方法

    公开(公告)号：US20090098706A1

    公开(公告)日：2009-04-16

    申请号：US11871602

    申请日：2007-10-12

    申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    IPC分类号： H01L21/762

    CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。