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公开(公告)号：US4698545A
公开(公告)日：1987-10-06
申请号：US776808
申请日：1985-09-17
IPC分类号： H01J29/07
CPC分类号： H01J29/07 , H01J2229/0733 , H01J2229/0783
摘要： Color picture tube in which a tube element, e.g., the shadow mask, is constituted by an Fe alloy to which 25-45 wt % of Ni and at least some Cr are added. A Cr rich layer is formed on the tube element surface and black oxide film with a spinel structure containing Cr is formed on the surface of this film.
摘要翻译： 彩色显象管，其中诸如荫罩的管元件由添加有25-45重量％的Ni和至少一些Cr的Fe合金构成。 在管元件表面上形成富Cr层，并且在该膜的表面上形成具有包含Cr的尖晶石结构的黑色氧化物膜。
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公开(公告)号：US4724012A
公开(公告)日：1988-02-09
申请号：US773235
申请日：1985-09-06
IPC分类号： C22C38/00 , C21D6/00 , C21D8/00 , C21D9/46 , C22C38/18 , C22C38/40 , C22C38/52 , H01J29/02 , H01J29/07 , C21D8/10
CPC分类号： C22C38/40 , C22C38/52 , H01J29/02 , H01J29/07 , H01J2229/0733
摘要： In-tube component material for an electronic tube such as a color cathode ray tube, of low thermal expansion coefficient and grain size 2,000-40,000 grains/mm.sup.2, containing Fe as the main constituent and 25-45 wt % Ni, 0.3-10 wt % Cr, and 0-10 wt % Co, and a method of manufacturing it.
摘要翻译： 用于诸如彩色阴极射线管的电子管的管内部件材料，热膨胀系数低，晶粒尺寸为2,000-40,000粒/ mm2，以Fe为主要成分，25-45wt％的Ni，0.3-10wt ％Cr和0〜10重量％Co，及其制造方法。
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公开(公告)号：US4551975A
公开(公告)日：1985-11-12
申请号：US681126
申请日：1984-12-13
申请人： Masao Yamamoto , Tetsuo Fujiwara
发明人： Masao Yamamoto , Tetsuo Fujiwara
CPC分类号： H01H61/0107 , B25J9/1085
摘要： An actuator is arranged such that an operation stroke is obtained by a shape memory element made of a shape memory alloy member for recovering a memorized shape when the shape memory alloy member is heated, and that shape recovery control of the shape memory element is performed by Joule heat generated by a current supplied thereto. The shape memory element of this actuator has a mechanism such as conductive layers made of copper-plated layers covering part of the surface of the shape memory alloy. This mechanism decreases an electrical resistance of at least one portion of the element such that it is smaller than the electrical resistance of any other portion thereof. The conductive layers contribute to the partial shape recovery control of the shape memory element with high precision.
摘要翻译： 致动器被布置成使得通过由形状记忆合金构件形成的形状记忆元件获得操作行程，用于当形状记忆合金构件被加热时恢复记忆形状，并且形状记忆元件的形状恢复控制由 由提供给其的电流产生的焦耳热。 该致动器的形状记忆元件具有诸如覆盖形状记忆合金的表面的一部分的由镀铜层形成的导电层的机构。 该机构降低元件的至少一部分的电阻，使得其小于其任何其它部分的电阻。 导电层有助于高精度地形状记忆元件的局部形状恢复控制。
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公开(公告)号：US4935915A
公开(公告)日：1990-06-19
申请号：US324458
申请日：1989-03-16
IPC分类号： G11B7/125 , G11B11/105 , G11B19/02
CPC分类号： G11B7/126 , G11B11/10532 , G11B19/02
摘要： A beam controller for controlling a semiconductor laser provided in an optical recording/playback apparatus includes first and second current sources for driving the semiconductor laser at a low level (play-back mode) and/or at a high level (recording or erasing mode). The first and second current sources are controlled to have stable power automatically by a first and second auto-power circuits, respectively. The first and second auto-power control circuits include a sample-hold circuit which stores an output signal from a low-pass filter. This enables the beam controller to avoid the transition response problems of the low-pass filter. A switching circuit is also included to select either the stored low-pass filter signal on the present low-pass filter signal.
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公开(公告)号：US4843604A
公开(公告)日：1989-06-27
申请号：US919672
申请日：1986-10-16
IPC分类号： G11B7/125 , G11B11/105 , G11B19/02
CPC分类号： G11B7/126 , G11B11/10532 , G11B19/02
摘要： A beam controller for controlling a semiconductor laser included in an optical recording-play-back apparatus. The beam controller is comprised of first and second current sources for driving the semiconductor laser at a low level during a play-back mode and at a high level during an erasing mode. The first and second current sources are respectively automatically controlled by a first and second auto-power control circuit to provide stable power outputs.
摘要翻译： 一种用于控制包括在光学记录重放装置中的半导体激光器的光束控制器。 光束控制器包括第一和第二电流源，用于在回放模式期间以低电平驱动半导体激光器，并且在擦除模式期间处于高电平。 第一和第二电流源分别由第一和第二自动功率控制电路自动控制以提供稳定的功率输出。
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6.发明授权Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus 有权半导体装置，半导体装置的制造方法，半导体制造和检查装置以及检查装置公开(公告)号：US08946895B2
公开(公告)日：2015-02-03
申请号：US12389479
申请日：2009-02-20
申请人： Takahiko Kato , Hiroshi Nakano , Haruo Akahoshi , Yuuji Takada , Yoshimi Sudo , Tetsuo Fujiwara , Itaru Kanno , Tomoryo Shono , Yukinori Hirose
发明人： Takahiko Kato , Hiroshi Nakano , Haruo Akahoshi , Yuuji Takada , Yoshimi Sudo , Tetsuo Fujiwara , Itaru Kanno , Tomoryo Shono , Yukinori Hirose
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L22/12 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
摘要翻译： 具有包括可以减小表面空隙的碱性晶体结构的Cu布线的半导体器件和用于半导体器件的检查技术。 在半导体装置中，通过指定阻挡层和种子层，并设定具有一致位点网格（CSL）边界的占有比例（频率），表面空隙可以降低到当前实用水平的1/10以下，具有 对于Cu布线的所有晶界，晶界Sigma值为27以下，为60％以上。 或者，可以通过指定阻挡层和种子层并且将具有晶界Sigma值3的重合位点晶格（CSL）边界的占有比例（频率）设置为全部晶粒，可以获得类似的表面空隙降低效果 Cu布线的边界为40％以上。
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公开(公告)号：US06917065B2
公开(公告)日：2005-07-12
申请号：US10681173
申请日：2003-10-09
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L27/11502 , H01L27/10805 , H01L27/1085 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.
摘要翻译： 具有顶电极，铁电薄膜和底电极的铁电电容器的特征在于，所述铁电薄膜是含有Pb的钙钛矿型氧化物，所述上下电极含有由Pt构成的金属间化合物 和铅。 电子设备设有所述铁电电容器。 这种结构旨在解决以下问题。 在非易失性铁电存储器（FeRAM）中，由于在处理期间释放的氢或由于PZT向电极扩散Pb而在PZT和电极之间的界面附近出现劣化层。 在电极和铁电薄膜之间的界面产生由于晶格常数的差异引起的应力。 劣化层和界面应力劣化铁电电容器的初始极化特性，并且在开关周期后极大地降低极化特性。
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8.发明授权Method of forming capacitor with ruthenium top and bottom electrodes by MOCVD 失效通过MOCVD形成具有钌顶部和底部电极的电容器的方法公开(公告)号：US07071053B2
公开(公告)日：2006-07-04
申请号：US10852121
申请日：2004-05-25
IPC分类号： H01L21/8242
摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
摘要翻译： 提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。 通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，该底部电极46和顶部电极48包括具有100％阶梯覆盖的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上， 通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。
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公开(公告)号：US06821845B1
公开(公告)日：2004-11-23
申请号：US09806861
申请日：2001-04-05
IPC分类号： H01L218242
摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
摘要翻译： 提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。 通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，底部电极46和顶部电极48包括具有100％台阶覆盖率的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上， 通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。
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公开(公告)号：US06483167B1
公开(公告)日：2002-11-19
申请号：US09644716
申请日：2000-08-23
申请人： Toshihide Nabatame , Masaru Kadoshima , Takaaki Suzuki , Tetsuo Fujiwara , Seiji Watahiki , Yasuhiko Murata , Mitsuo Hayashibara
发明人： Toshihide Nabatame , Masaru Kadoshima , Takaaki Suzuki , Tetsuo Fujiwara , Seiji Watahiki , Yasuhiko Murata , Mitsuo Hayashibara
IPC分类号： H01L2900
摘要： In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.
摘要翻译： 在半导体装置及其制造方法中，使用这样的技术来防止在进行底部电极紧密堆积的热处理过程中发生的底部电极的膜分离和用于产生电介质结晶的热处理工艺。 在制造方法中，在SiO2绝缘层和凹孔的内壁之间形成包含绝缘体的胶层。 SiO 2层14位于Si基板11上，形成Si塞12和阻挡层13。 在SiO 2绝缘层15的孔的内壁上形成胶层16，在阻挡层13和胶层16上形成包含Ru的底部电极17.包含BST的电介质膜18和顶部电极19包括 Ru依次层叠在底部电极17上，形成具有底部电极17的电介质器件。
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