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公开(公告)号：US5733427A
公开(公告)日：1998-03-31
申请号：US413898
申请日：1995-03-30
申请人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
发明人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
CPC分类号： C04B35/58092 , C04B35/645 , C04B35/65 , C23C14/3414
摘要： A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
摘要翻译： 由具有组成为MSix的难熔金属硅化物形成的溅射靶，所述组合物包括颗粒形式的MSi2相的混合组成（M：选自W，Mo，Ti，Zr，Hf， Ni和Ta）和作为基质相的Si相。 在MSi2相和Si相之间的界面处形成具有预定厚度的界面层。 组成式MSix中的值X设定在2.0〜4.0的范围内，形成在MSi2相和Si相之间的界面层的厚度，组成的分散性，靶的密度比，电 Si相的电阻率和表面粗糙度被设定为预定值。 通过使用该目标，可以稳定地制造组合物分布均匀的均匀的高品质薄膜。
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公开(公告)号：US5447616A
公开(公告)日：1995-09-05
申请号：US166007
申请日：1993-12-14
申请人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
发明人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
CPC分类号： C04B35/58092 , C04B35/645 , C04B35/65 , C23C14/3414
摘要： A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
摘要翻译： 由具有组成为MSix的难熔金属硅化物形成的溅射靶，所述组合物包括颗粒形式的MSi2相的混合组成（M：选自W，Mo，Ti，Zr，Hf， Ni和Ta）和作为基质相的Si相。 在MSi2相和Si相之间的界面处形成具有预定厚度的界面层。 组成式MSix中的值X设定在2.0〜4.0的范围内，形成在MSi2相和Si相之间的界面层的厚度，组成的分散性，靶的密度比，电 Si相的电阻率和表面粗糙度被设定为预定值。 通过使用该目标，可以稳定地制造组合物分布均匀的均匀的高品质薄膜。
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公开(公告)号：US5294321A
公开(公告)日：1994-03-15
申请号：US974317
申请日：1993-11-10
申请人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
发明人： Michio Satou , Takashi Yamanobe , Mitsuo Kawai , Tatsuzo Kawaguchi , Kazuhiko Mitsuhashi , Toshiaki Mizutani
CPC分类号： C04B35/58092 , C04B35/645 , C04B35/65 , C23C14/3414
摘要： A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
摘要翻译： 由具有组成为MSix的难熔金属硅化物形成的溅射靶，所述组合物包括颗粒形式的MSi2相的混合组成（M：选自W，Mo，Ti，Zr，Hf， Ni和Ta）和作为基质相的Si相。 在MSi2相和Si相之间的界面处形成具有预定厚度的界面层。 组成式MSix中的值X设定在2.0〜4.0的范围内，形成在MSi2相和Si相之间的界面层的厚度，组成的分散性，靶的密度比，电 Si相的电阻率和表面粗糙度被设定为预定值。 通过使用该目标，可以稳定地制造组合物分布均匀的均匀的高品质薄膜。
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公开(公告)号：US20070181556A1
公开(公告)日：2007-08-09
申请号：US11508156
申请日：2006-08-23
申请人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kenji Matsuda , Kinji Yamada , Tomotaka Shinoda , Daohai Wang , Katsuya Okumura
发明人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kenji Matsuda , Kinji Yamada , Tomotaka Shinoda , Daohai Wang , Katsuya Okumura
IPC分类号： F27B5/14
CPC分类号： H01L28/55
摘要： Atmosphere in processing apparatus is adjusted to, for example, oxygen atmosphere, by gas supply source and the like. Interior of thermal processing apparatus is set to oxygen atmosphere and raised to predetermined temperature. A wafer boat containing wafer W having dielectric precursor layer formed is loaded into thermal processing apparatus at speed at which no defects are produced in wafer W. Thereafter, reaction tube of thermal processing apparatus has its internal temperature raised to baking temperature, to perform baking for predetermined time. The wafer W is cooled to predetermined temperature in thermal processing apparatus and then to room temperature in processing apparatus, and carried out from processing apparatus. Before dielectric precursor layer is baked, it is maintained for predetermined time at temperature higher than temperature at which solvent in dielectric precursor layer is volatilized and lower than temperature at which dielectric precursor layer starts crystallization to vaporize residual solvent.
摘要翻译： 处理装置中的气氛通过气体供给源等调节为例如氧气氛。 热处理装置的内部设定为氧气氛并升温至规定温度。 包含形成有电介质前体层的晶片W的晶片舟以晶片W中没有产生缺陷的速度装载到热处理装置中。之后，热处理装置的反应管的内部温度升高到烘烤温度，进行烘烤 预定时间 将晶片W在热处理装置中冷却至规定温度，然后在处理装置中冷却至室温，并从处理装置进行。 在电介质前体层被烘烤之前，在高于电介质前体层中的溶剂挥发并且低于电介质前体层开始结晶以蒸发残留溶剂的温度的温度下将其保持预定时间。
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公开(公告)号：US07742277B2
公开(公告)日：2010-06-22
申请号：US11508204
申请日：2006-08-23
申请人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
发明人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
CPC分类号： H01L28/65 , H01L27/11507 , H01L28/55 , Y10T29/435
摘要： A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
摘要翻译： 电介质膜电容器包括具有开口并由包括铂的材料形成的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜和设置在电介质膜上的上电极。 下部电极的平面面积为电介质膜的形成区域的面积的50％以上。 电介质膜电容器包括由包括铂的材料形成的厚度为10至100nm的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜，以及设置在电介质上的上电极 电影。
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公开(公告)号：US08247289B2
公开(公告)日：2012-08-21
申请号：US11508141
申请日：2006-08-23
申请人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
发明人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/00
CPC分类号： H01L23/50 , H01G4/228 , H01G4/33 , H01L23/481 , H01L24/81 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H05K1/162 , H05K3/002 , H05K2201/09509 , H05K2201/096 , H05K2201/10378
摘要： A capacitor having a high quality and a manufacturing method of the same are provided.A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
摘要翻译： 提供了具有高质量的电容器及其制造方法。 电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极 ，上电极的开口部分和电介质层的开口部分。 通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。 通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等
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公开(公告)号：US4485000A
公开(公告)日：1984-11-27
申请号：US603683
申请日：1984-04-25
IPC分类号： C23C14/50 , C23C14/34 , H01J37/34 , H01L21/203 , H01L21/285 , H01L21/31 , C23C15/00
CPC分类号： H01J37/3423 , C23C14/3407 , H01J37/34 , H01J37/3429
摘要： In a sputtering target supporting device for fixing, to a common electrode, a plurality of beams forming a mosaic target used for co-sputtering, at least one pressing mechanism is provided exclusively for each of the beams to press the respective beam against the common electrode by means of the respective pressing mechanism provided therefor.
摘要翻译： 在用于将公共电极固定到形成用于共溅射的镶嵌目标的多个光束的溅射靶支撑装置中，仅为每个光束提供至少一个按压机构，以将各个光束压在公共电极上 借助于其设置的相应的按压机构。
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公开(公告)号：US20070181928A1
公开(公告)日：2007-08-09
申请号：US11508141
申请日：2006-08-23
申请人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
发明人： Yoshiki Yamanishi , Muneo Harada , Takahiro Kitano , Tatsuzo Kawaguchi , Yoshihiro Hirota , Kinji Yamada , Tomotaka Shinoda , Katsuya Okumura , Shuichi Kawano
IPC分类号： H01L29/94
CPC分类号： H01L23/50 , H01G4/228 , H01G4/33 , H01L23/481 , H01L24/81 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H05K1/162 , H05K3/002 , H05K2201/09509 , H05K2201/096 , H05K2201/10378
摘要： A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
摘要翻译： 提供了具有高质量的电容器及其制造方法。 电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极 ，上电极的开口部分和电介质层的开口部分。 通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。 通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等
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公开(公告)号：US20070126041A1
公开(公告)日：2007-06-07
申请号：US11508204
申请日：2006-08-23
申请人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
发明人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
CPC分类号： H01L28/65 , H01L27/11507 , H01L28/55 , Y10T29/435
摘要： A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
摘要翻译： 电介质膜电容器包括具有开口并由包括铂的材料形成的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜和设置在电介质膜上的上电极。 下部电极的平面面积为电介质膜的形成区域的面积的50％以上。 电介质膜电容器包括由包括铂的材料形成的厚度为10至100nm的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜，以及设置在电介质上的上电极 电影。
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