公开(公告)号：US07389476B2

公开(公告)日：2008-06-17

申请号：US10636589

申请日：2003-08-08

申请人： Michiru Senda ,  Masayuki Koga ,  Masahiro Okuyama ,  Ryoichi Yokoyama ,  Isao Akima

发明人： Michiru Senda ,  Masayuki Koga ,  Masahiro Okuyama ,  Ryoichi Yokoyama ,  Isao Akima

IPC分类号： G06F15/00 ,  G06F13/00

CPC分类号： G02F1/1335 ,  G02F1/1333 ,  G02F1/133555 ,  G02F1/1345 ,  G02F1/1368 ,  G02F2001/133342 ,  G02F2001/133616 ,  G06F3/1423 ,  G09F9/35 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0289 ,  H04M1/0214 ,  H04M1/0245 ,  H04M2250/16

摘要： A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

摘要翻译： 获得当包括多个显示面板时允许进一步小型化的显示器。 该显示器包括形成在基板上的第一显示面板和形成在与形成有第一显示面板的区域不同的区域上的同一基板上的第二显示面板。 因此，与具有形成在不同基板上的第一显示面板和第二显示面板相比，显示器可以进一步小型化。

公开(公告)号：US07164404B2

公开(公告)日：2007-01-16

申请号：US10625843

申请日：2003-07-24

申请人： Michiru Senda ,  Isao Akima

发明人： Michiru Senda ,  Isao Akima

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/32 ,  G09G3/3659 ,  G09G3/3688 ,  G09G2300/0828 ,  G09G2300/0876 ,  G09G2310/027 ,  G09G2340/145

摘要： A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

摘要翻译： 数字图像信号通过漏极信号线串行传输到每个像素。 数字图像信号在像素选择晶体管被采样，从串行信号转换成并行信号，然后由DA转换器转换为模拟图像信号。 该DA转换器包括以加权电容比耦合到像素电极的多个电容器电极和用于响应于数字图像信号向多个电容器电极提供周期性时钟信号的时钟提供部分。 模拟图像信号被施加到像素电极。 这简化了像素的外围电路的配置，并且因此减小了面板的框架面积和布线数量。

公开(公告)号：US5266834A

公开(公告)日：1993-11-30

申请号：US915761

申请日：1992-07-21

申请人： Kunihiko Nishi ,  Michio Tanimoto ,  Toshihiro Yasuhara ,  Katsuhiro Tabata ,  Yasuhiro Yoshikawa ,  Isao Akima ,  Souichi Kunito ,  Toshio Nosaka ,  Hideaki Nakamura

发明人： Kunihiko Nishi ,  Michio Tanimoto ,  Toshihiro Yasuhara ,  Katsuhiro Tabata ,  Yasuhiro Yoshikawa ,  Isao Akima ,  Souichi Kunito ,  Toshio Nosaka ,  Hideaki Nakamura

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/02

CPC分类号： H01L23/4951 ,  H01L23/49568 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511

摘要： A package is provided for achieving higher packing density and higher circuit integration of memories, in particular, a structure is provided having a plurality of thin, surface mount packages which are stacked up. Each of the laminated packages includes a semiconductor pellet, leads fixed to the front surface of the pellet, a radiating plate fixed to the rear surface of the same, and a resin mold member. To achieve a stabilized laminated structure, the mold member is shaped into a convex form on the front side of the pellet and into a concave form on the rear side of the same, so that the concave portion of one package can engage with the convex portion of another package.

摘要翻译： 提供了用于实现更高的堆积密度和更高的存储器电路集成的封装，特别地，提供了具有堆叠的多个薄的表面贴装封装的结构。 每个层叠包装包括半导体颗粒，固定在颗粒的前表面的引线，固定到其后表面的散热板和树脂模制构件。 为了实现稳定的层压结构，模具构件在颗粒的前侧成形为凸形，并且在其后侧成为凹形，使得一个包装的凹部能够与凸部接合 的另一个包。

公开(公告)号：US20080229316A1

公开(公告)日：2008-09-18

申请号：US12045206

申请日：2008-03-10

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G06F9/46

CPC分类号： G06T5/20

摘要： A data processing device includes: an execution unit; and a memory unit, wherein the memory unit stores a plurality of pre-processing data on which a processing is to be rendered at a plurality of times prior to a specified time; (1) when a value of specified pre-processing data at the specified time is in a range between a maximum value and a minimum value among values of the plurality of pre-processing data, the execution unit renders the processing on the specified pre-processing data; and (2) when the value of the specified pre-processing data is greater than the maximum value or smaller than the minimum value, the execution unit renders the processing on an arbitrary value that is deemed substantively in the range between the maximum value and the minimum value, instead of the value of the specified pre-processing data.

摘要翻译： 一种数据处理装置，包括：执行单元; 以及存储单元，其中所述存储单元在指定时间之前多次存储要在其上呈现处理的多个预处理数据; （1）在所述规定时间的指定预处理数据的值处于所述多个预处理数据的值之间的最大值与最小值之间的范围内时，所述执行单元对所述预处理数据进行处理， 处理数据; 和（2）当指定的预处理数据的值大于最大值或小于最小值时，执行单元对在最大值和最小值之间的范围内实质上认为的任意值进行处理 最小值，而不是指定的预处理数据的值。

公开(公告)号：US20060119553A1

公开(公告)日：2006-06-08

申请号：US11285830

申请日：2005-11-22

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G09G3/30

CPC分类号： G09G3/32 ,  G09G3/2014 ,  G09G2310/0272 ,  G09G2320/066 ,  G09G2330/02

摘要： A display module enabling recognition of an image when the entire screen is bright (or dark). A current drive circuit includes a current amount control circuit for controlling the amount of current supplied from a high potential power supply to a transmission path in response to a current control signal. A drive current generation circuit controls the amount of current flowing through a transmission line in accordance with a gray scale value of video data based on RGB pulse width modulation signals. Current, which corresponds to the difference between the current of the current amount control circuit and the current controlled by the drive current generation circuit, flows through the transmission line. When using the drive current of the drive current generation circuit as a base current, the current amount control circuit adds current to the drive current with the current control signal.

摘要翻译： 当整个屏幕亮（或暗）时，能够识别图像的显示模块。 电流驱动电路包括电流量控制电路，用于响应于电流控制信号控制从高电位电源提供给传输路径的电流量。 驱动电流产生电路根据RGB脉宽调制信号，根据视频数据的灰度值控制流经传输线的电流量。 对应于电流量控制电路的电流与由驱动电流产生电路控制的电流之间的差值的电流流过传输线。 当使用驱动电流产生电路的驱动电流作为基极电流时，电流量控制电路利用电流控制信号将电流加到驱动电流上。

公开(公告)号：US20050231535A1

公开(公告)日：2005-10-20

申请号：US11105581

申请日：2005-04-14

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/22 ,  G09G3/30 ,  G09G3/32 ,  H04N5/66 ,  H04N5/70 ,  H05B33/14 ,  G09G5/00

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/22 ,  G09G3/32 ,  G09G3/3241 ,  G09G2320/0233

摘要： The variation of the electric current fed to the luminescent element is prevented in the display device with the electric current driven luminescent element, achieving uniform display brightness. The pulse width modulation circuit 10 generating a pulse width modulation signal SRP, the pulse of which is modulated for a certain period according to the image data, and the electric current generation circuit 20 generating the pulse current I corresponding the pulse width modulation signal are formed. The pulse current I is supplied to the electric current driven luminescent elements L1 and L2 through the pixel selection TFT 51, 52. Since the pulse current I is stable and at a certain level, it is not influenced by the variation among the pixels due to the manufacturing process, achieving uniform display brightness and improved display quality.

摘要翻译： 在具有电流驱动的发光元件的显示装置中，防止馈送到发光元件的电流的变化，实现均匀的显示亮度。 形成脉冲宽度调制电路10，其产生脉冲宽度调制信号SRP，脉冲宽度调制信号SRP根据图像数据调制一定时间，电流产生电路20产生对应于脉宽调制信号的脉冲电流I 。 脉冲电流I通过像素选择TFT51,52被提供给电流驱动发光元件L 1和L 2。 由于脉冲电流I稳定并处于一定水平，所以不受制造工艺中的像素之间的变化的影响，实现均匀的显示亮度和显示质量的提高。

公开(公告)号：US4509147A

公开(公告)日：1985-04-02

申请号：US383945

申请日：1982-06-01

申请人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

发明人： Nobuyoshi Tanimura ,  Sho Yamamoto ,  Kazuo Yoshizaki ,  Isao Akima

IPC分类号： G11C7/06 ,  G11C11/419 ,  H03F3/45 ,  H03F3/72 ,  G11C11/34

CPC分类号： H03F3/72 ,  G11C11/419 ,  G11C7/06 ,  H03F3/45475

摘要： In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained. The operating speed of the RAM can be raised owing to the fact that the dissymmetric type differential amplifier circuit having an active load circuit exhibits a comparatively high gain and the fact that the signal amplification by the balanced circuit is permitted.

摘要翻译： 在静态RAM中，读出放大器包括第一和第二非对称型差分放大器电路，每个差分放大器具有一对差分晶体管和有源负载电路，例如连接到差分晶体管的漏极的电流镜电路。 从存储单元发送的平衡信号中的一个被提供给第一非对称型差分放大器电路的非反相输入端子和第二非对称型差分放大器电路的反相输入端子。 所述平衡信号中的另一个被施加到第一和第二非对称型差分放大器电路的剩余输入端。 结果，尽管不能从每个非对称型差分放大器电路输出平衡信号，但是可以获得放大的平衡信号。 由于具有有源负载电路的非对称型差分放大器电路具有相对较高的增益以及允许由平衡电路进行信号放大的事实，所以可以提高RAM的工作速度。

公开(公告)号：US20080187133A1

公开(公告)日：2008-08-07

申请号：US12022244

申请日：2008-01-30

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： H04L9/28

CPC分类号： G06F21/72

摘要： An encryption processing circuit includes: a rewritable ferroelectric memory including an encryption table containing one or more data codes paired with encryption codes that are the data codes encrypted, a first region for storing the encryption codes, and a second region for storing the data codes, wherein, when the encryption code is stored in the first region, the encryption table is searched through and the data code pairing with the encryption code is outputted to the second region, and when the data code is stored in the second region, the encryption table is searched through and the encryption code paring with the data code is outputted to the first region.

摘要翻译： 一种加密处理电路包括：可重写铁电存储器，包括包含与作为加密的数据代码的加密码配对的一个或多个数据代码的加密表，用于存储加密代码的第一区域和用于存储数据代码的第二区域， 其特征在于，当在第一区域中存储加密代码时，搜索加密表，并将与加密代码配对的数据代码输出到第二区域，并且当数据代码存储在第二区域中时，加密表 并且将与数据代码对应的加密代码输出到第一区域。

公开(公告)号：US20060132493A1

公开(公告)日：2006-06-22

申请号：US11286174

申请日：2005-11-22

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G06F13/14

CPC分类号： G09G3/006 ,  G09G3/2092 ,  G09G2320/0233 ,  G09G2330/08 ,  G09G2360/18

摘要： A display apparatus includes a video signal processing unit, a display panel, and a bidirectional bus. The video signal processing unit transmits a video signal via the bidirectional bus. The display panel displays an image in accordance with the video signal. The video signal processing unit and the display module are connected to the bidirectional bus. When a tester is connected to the bidirectional bus, the bidirectional bus directly connects the tester to the video signal processing unit and the display module. The tester separately tests the video signal processing unit and the display panel after the display apparatus is assembled.

摘要翻译： 显示装置包括视频信号处理单元，显示面板和双向总线。 视频信号处理单元经由双向总线发送视频信号。 显示面板根据视频信号显示图像。 视频信号处理单元和显示模块连接到双向总线。 当测试仪连接到双向总线时，双向总线将测试仪直接连接到视频信号处理单元和显示模块。 显示装置组装后，测试仪分别测试视频信号处理单元和显示面板。

公开(公告)号：US20060119550A1

公开(公告)日：2006-06-08

申请号：US11281894

申请日：2005-11-18

申请人： Isao Akima

发明人： Isao Akima

IPC分类号： G09G3/30

CPC分类号： G09G3/2096 ,  G09G3/3611 ,  G09G2330/06

摘要： A number of data transmission lines between a controller LSI and a display device and external devices is reduced to reduce a wiring space in a portable information device to realize further size reduction of the device. A controller LSI side transmission/reception circuit is included in the controller LSI, while an external device selection and transmission circuit and a display unit are included in a display device. And two-way transmission lines are provided between the controller LSI side transmission/reception circuit and the external device selection and transmission circuit. Various kinds of external devices MD0-MD3 for human interface are connected to the external device selection and transmission circuit.

摘要翻译： 控制器LSI与显示装置之间的数据传输线和外部设备的数量减少，以减少便携式信息设备中的布线空间，从而进一步减小设备的尺寸。 控制器LSI侧发送/接收电路包括在控制器LSI中，而外部设备选择和发送电路和显示单元包括在显示设备中。 并且在控制器LSI侧发送/接收电路和外部设备选择和发送电路之间提供双向传输线。 各种外部设备MD 0 -MD 3用于人机界面连接到外部设备选择和传输电路。