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    SETTING A POWER MODE BASED ON A WORKLOAD LEVEL IN A MEMORY SUB-SYSTEM
    1.
    发明申请
    SETTING A POWER MODE BASED ON A WORKLOAD LEVEL IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210294407A1

    公开(公告)日：2021-09-23

    申请号：US16821579

    申请日：2020-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan Parry

    IPC: G06F1/3234 ,  G06F1/3296 ,  G11C5/14

    Abstract: A workload level in an incoming request queue is determined based on one or more operations requested by a host system for execution by a memory sub-system. Based on the workload level in the incoming request queue, a set of memory dies of the memory sub-system to be activated for execution of the one or more operations is identified. Based on a power budget level, a power mode configuration for a memory die of the set of memory dies is determined. One or more parameters of the memory die are configured to establish the power mode configuration.

    SYSTEMS FOR PROVIDING ACCESS TO PROTECTED MEMORY
    2.
    发明申请
    SYSTEMS FOR PROVIDING ACCESS TO PROTECTED MEMORY 审中-公开

    公开(公告)号：US20200210596A1

    公开(公告)日：2020-07-02

    申请号：US16236754

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan Parry

    IPC: G06F21/60 ,  H04L9/08

    Abstract: A memory device embodiment may include an array of non-volatile memory cells including a protected memory region. The protected memory region may include a dedicated sub region established by a host. The memory device embodiment may also include a memory controller configured to wipe the protected memory region or execute other security functions by issuing an authenticated data write command to the dedicated sub region of the protected region. Issuing the authenticated data write command may include signing the command with a key shared with the host that established the sub region.

    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    3.
    发明申请
    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES 审中-公开

    公开(公告)号：US20200210080A1

    公开(公告)日：2020-07-02

    申请号：US16237134

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

    MANAGEMENT OF POWER DURING MEMORY DEVICE RESET AND INITIALIZATION
    7.
    发明申请
    MANAGEMENT OF POWER DURING MEMORY DEVICE RESET AND INITIALIZATION 有权

    公开(公告)号：US20220100431A1

    公开(公告)日：2022-03-31

    申请号：US17549181

    申请日：2021-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan Parry

    IPC: G06F3/06 ,  G11C16/26

    Abstract: A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.

    MANAGEMENT OF POWER DURING MEMORY DEVICE RESET AND INITIALIZATION
    8.
    发明申请
    MANAGEMENT OF POWER DURING MEMORY DEVICE RESET AND INITIALIZATION 有权

    公开(公告)号：US20210357149A1

    公开(公告)日：2021-11-18

    申请号：US16875464

    申请日：2020-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan Parry

    IPC: G06F3/06 ,  G11C16/26

    Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.

    Systems for providing access to protected memory
    10.
    发明授权
    Systems for providing access to protected memory 有权

    公开(公告)号：US11321468B2

    公开(公告)日：2022-05-03

    申请号：US16236754

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan Parry

    IPC: G06F21/60 ,  H04L9/08

    Abstract: A memory device embodiment may include an array of non-volatile memory cells including a protected memory region. The protected memory region may include a dedicated sub region established by a host. The memory device embodiment may also include a memory controller configured to wipe the protected memory region or execute other security functions by issuing an authenticated data write command to the dedicated sub region of the protected region. Issuing the authenticated data write command may include signing the command with a key shared with the host that established the sub region.

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